Commit 27c9d763 authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779a0: Add RPC support 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211006085836.42155-3-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6f21d145

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+32 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ enum rcar_r8a779a0_clk_types { 
	CLK_TYPE_R8A779A0_SD,

	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */

	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */

	CLK_TYPE_R8A779A0_RPCSRC,

	CLK_TYPE_R8A779A0_RPC,

	CLK_TYPE_R8A779A0_RPCD2,

};



struct rcar_r8a779a0_cpg_pll_config {
@@ -125,6 +128,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED(".s3",		CLK_S3,		CLK_PLL1_DIV2,	4, 1),

	DEF_FIXED(".sdsrc",		CLK_SDSRC,	CLK_PLL5_DIV4,	1, 1),

	DEF_RATE(".oco",		CLK_OCO,	32768),

	DEF_BASE(".rpcsrc",	 CLK_RPCSRC,	   CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),

	DEF_BASE("rpc",		 R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	 R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,

		 R8A779A0_CLK_RPC),



	/* Core Clock Outputs */

	DEF_Z("z0",		R8A779A0_CLK_Z0,	CLK_PLL20,	2, 0),
@@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("msi3",		621,	R8A779A0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779A0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779A0_CLK_MSO),

	DEF_MOD("rpc-if",	629,	R8A779A0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),
@@ -414,6 +422,15 @@ static struct clk * __init cpg_z_clk_register(const char *name, 
	return clk;

}



/*

 * RPC Clocks

 */

#define CPG_RPCCKCR 0x874



static const struct clk_div_table cpg_rpcsrc_div_table[] = {

	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },

};



static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,

	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,

	struct clk **clks, void __iomem *base,
@@ -481,6 +498,21 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 
		div = cpg_pll_config->osc_prediv * core->div;

		break;



	case CLK_TYPE_R8A779A0_RPCSRC:

		return clk_register_divider_table(NULL, core->name,

						  __clk_get_name(parent), 0,

						  base + CPG_RPCCKCR, 3, 2, 0,

						  cpg_rpcsrc_div_table,

						  &cpg_lock);



	case CLK_TYPE_R8A779A0_RPC:

		return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,

					    __clk_get_name(parent), notifiers);



	case CLK_TYPE_R8A779A0_RPCD2:

		return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,

					      __clk_get_name(parent));



	default:

		return ERR_PTR(-EINVAL);

	}