Commit 27c92c60 authored by Quentin Schulz's avatar Quentin Schulz Committed by Heiko Stuebner
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arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30 



The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are
2-channel I2S/PCM controllers handled by the same controller driver, and
i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller
driver.

This adds the device tree node required to enable I2S0 on PX30.

This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX
(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board.

Signed-off-by: default avatarQuentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1c33f850

arch/arm64/boot/dts/rockchip/px30.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -365,6 +365,28 @@ 
		status = "disabled";

	};



	i2s0_8ch: i2s@ff060000 {

		compatible = "rockchip,px30-i2s-tdm";

		reg = <0x0 0xff060000 0x0 0x1000>;

		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;

		clock-names = "mclk_tx", "mclk_rx", "hclk";

		dmas = <&dmac 16>, <&dmac 17>;

		dma-names = "tx", "rx";

		rockchip,grf = <&grf>;

		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;

		reset-names = "tx-m", "rx-m";

		pinctrl-names = "default";

		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx

			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx

			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0

			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1

			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2

			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;

		#sound-dai-cells = <0>;

		status = "disabled";

	};



	i2s1_2ch: i2s@ff070000 {

		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";

		reg = <0x0 0xff070000 0x0 0x1000>;