Loading arch/ia64/mm/init.c +1 −7 Original line number Diff line number Diff line Loading @@ -58,7 +58,6 @@ __ia64_sync_icache_dcache (pte_t pte) { unsigned long addr; struct page *page; unsigned long order; page = pte_page(pte); addr = (unsigned long) page_address(page); Loading @@ -66,12 +65,7 @@ __ia64_sync_icache_dcache (pte_t pte) if (test_bit(PG_arch_1, &page->flags)) return; /* i-cache is already coherent with d-cache */ if (PageCompound(page)) { order = compound_order(page); flush_icache_range(addr, addr + (1UL << order << PAGE_SHIFT)); } else flush_icache_range(addr, addr + PAGE_SIZE); flush_icache_range(addr, addr + (PAGE_SIZE << compound_order(page))); set_bit(PG_arch_1, &page->flags); /* mark page as clean */ } Loading Loading
arch/ia64/mm/init.c +1 −7 Original line number Diff line number Diff line Loading @@ -58,7 +58,6 @@ __ia64_sync_icache_dcache (pte_t pte) { unsigned long addr; struct page *page; unsigned long order; page = pte_page(pte); addr = (unsigned long) page_address(page); Loading @@ -66,12 +65,7 @@ __ia64_sync_icache_dcache (pte_t pte) if (test_bit(PG_arch_1, &page->flags)) return; /* i-cache is already coherent with d-cache */ if (PageCompound(page)) { order = compound_order(page); flush_icache_range(addr, addr + (1UL << order << PAGE_SHIFT)); } else flush_icache_range(addr, addr + PAGE_SIZE); flush_icache_range(addr, addr + (PAGE_SIZE << compound_order(page))); set_bit(PG_arch_1, &page->flags); /* mark page as clean */ } Loading