Commit 27142312 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix dcn3.1x mode validation on high bandwidth config 



[why]
1. correct dram_channel_width (was hard coded to 4 for 32bit)
2. use dm's is_hvm_enable status flag for hostvm_en input for dml.
3. add a function to override to all dcn3.1x.

Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5b8f9dea

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+3 −1
Original line number Diff line number Diff line
@@ -609,8 +609,10 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk 
	}



	bw_params->vram_type = bios_info->memory_type;

	bw_params->num_channels = bios_info->ma_channel_number;



	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;

	//bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width;

	bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;

	for (i = 0; i < WM_SET_COUNT; i++) {

		bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+1 −0
Original line number Diff line number Diff line
@@ -553,6 +553,7 @@ static void dcn316_clk_mgr_helper_populate_bw_params( 


	bw_params->vram_type = bios_info->memory_type;

	bw_params->num_channels = bios_info->ma_channel_number;

	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;



	for (i = 0; i < WM_SET_COUNT; i++) {

		bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+26 −7
Original line number Diff line number Diff line
@@ -1639,6 +1639,31 @@ static bool is_dual_plane(enum surface_pixel_format format) 
	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;

}



int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

					  struct dc_state *context,

					  display_e2e_pipe_params_st *pipes,

					  bool fast_validate)

{

	uint32_t pipe_cnt;

	int i;



	dc_assert_fp_enabled();



	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);



	for (i = 0; i < pipe_cnt; i++) {

		pipes[i].pipe.src.gpuvm = 1;

		if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {

			//pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

			pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;

		} else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)

			pipes[i].pipe.src.hostvm = false;

		else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)

			pipes[i].pipe.src.hostvm = true;

	}

	return pipe_cnt;

}



int dcn31_populate_dml_pipes_from_context(

	struct dc *dc, struct dc_state *context,

	display_e2e_pipe_params_st *pipes,
@@ -1650,7 +1675,7 @@ int dcn31_populate_dml_pipes_from_context( 
	bool upscaled = false;



	DC_FP_START();

	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	DC_FP_END();



	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1680,12 +1705,6 @@ int dcn31_populate_dml_pipes_from_context( 
		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);

		DC_FP_END();



		if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)

			pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

		else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)

			pipes[pipe_cnt].pipe.src.hostvm = false;

		else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)

			pipes[pipe_cnt].pipe.src.hostvm = true;



		if (pipes[pipe_cnt].dout.dsc_enable) {

			switch (timing->display_color_depth) {

drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c

+1 −2
Original line number Diff line number Diff line
@@ -1648,7 +1648,7 @@ static int dcn315_populate_dml_pipes_from_context( 
	const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;



	DC_FP_START();

	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	DC_FP_END();



	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1667,7 +1667,6 @@ static int dcn315_populate_dml_pipes_from_context( 
		pipes[pipe_cnt].pipe.src.immediate_flip = true;



		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

		pipes[pipe_cnt].pipe.src.gpuvm = true;

		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

		pipes[pipe_cnt].pipe.src.dcc_rate = 3;

		pipes[pipe_cnt].dout.dsc_input_bpc = 0;

drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c

+1 −2
Original line number Diff line number Diff line
@@ -1650,7 +1650,7 @@ static int dcn316_populate_dml_pipes_from_context( 
	const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;



	DC_FP_START();

	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	DC_FP_END();



	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1669,7 +1669,6 @@ static int dcn316_populate_dml_pipes_from_context( 
		pipes[pipe_cnt].pipe.src.immediate_flip = true;



		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

		pipes[pipe_cnt].pipe.src.gpuvm = true;

		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

		pipes[pipe_cnt].pipe.src.dcc_rate = 3;

		pipes[pipe_cnt].dout.dsc_input_bpc = 0;