Commit 2704e759 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Will Deacon
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dt-bindings: Add Arm SMMUv3 PMCG binding 



Add binding for the Arm SMMUv3 PMU. Each node represents a PMCG, and is
placed as a sibling node of the SMMU. Although the PMCGs registers may
be within the SMMU MMIO region, they are separate devices, and there can
be multiple PMCG devices for each SMMU (for example one for the TCU and
one for each TBU).

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/20211117144844.241072-2-jean-philippe@linaro.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d58071a8

Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Arm SMMUv3 Performance Monitor Counter Group



maintainers:

  - Will Deacon <will@kernel.org>

  - Robin Murphy <robin.murphy@arm.com>



description: |

  An SMMUv3 may have several Performance Monitor Counter Group (PMCG).

  They are standalone performance monitoring units that support both

  architected and IMPLEMENTATION DEFINED event counters.



properties:

  $nodename:

    pattern: "^pmu@[0-9a-f]*"

  compatible:

    oneOf:

      - items:

          - const: arm,mmu-600-pmcg

          - const: arm,smmu-v3-pmcg

      - const: arm,smmu-v3-pmcg



  reg:

    items:

      - description: Register page 0

      - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1

    minItems: 1



  interrupts:

    maxItems: 1



  msi-parent: true



required:

  - compatible

  - reg



anyOf:

  - required:

      - interrupts

  - required:

      - msi-parent



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    pmu@2b420000 {

            compatible = "arm,smmu-v3-pmcg";

            reg = <0x2b420000 0x1000>,

                  <0x2b430000 0x1000>;

            interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;

            msi-parent = <&its 0xff0000>;

    };



    pmu@2b440000 {

            compatible = "arm,smmu-v3-pmcg";

            reg = <0x2b440000 0x1000>,

                  <0x2b450000 0x1000>;

            interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;

            msi-parent = <&its 0xff0000>;

    };