Commit 26e8233b authored by Yanteng Si's avatar Yanteng Si Committed by Aichun Shi
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources

mainline inclusion
from mainline-v6.4-rc3
commit 34e82891
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IB4HZ4
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=34e82891d995ab89b494032c5ab0ee939cbb7524



-------------------------------------

Picking the changes from:

  c68e3d47 ("x86/include/asm/msr-index.h: Add IFS Array test bits")

Silencing these perf build warnings:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Intel-SIG: commit 34e82891 tools arch x86: Sync the msr-index.h copy with the kernel sources
Backport to fix IFS(In Field Scan) SAF(Scan At Field)

Signed-off-by: default avatarYanteng Si <siyanteng@loongson.cn>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: loongson-kernel@lists.loongnix.cn
Link: https://lore.kernel.org/r/05778ab3c168c8030f6b20e60375dc803f0cd300.1683712945.git.siyanteng@loongson.cn


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
[ Aichun Shi: amend commit log ]
Signed-off-by: default avatarAichun Shi <aichun.shi@intel.com>
parent 3faacfa7
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Original line number Diff line number Diff line
@@ -192,6 +192,11 @@
#define MSR_IA32_POWER_CTL		0x000001fc
#define MSR_IA32_POWER_CTL_BIT_EE	19

/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
#define MSR_INTEGRITY_CAPS			0x000002d9
#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT      2
#define MSR_INTEGRITY_CAPS_ARRAY_BIST          BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)

#define MSR_LBR_NHM_FROM		0x00000680
#define MSR_LBR_NHM_TO			0x000006c0
#define MSR_LBR_CORE_FROM		0x00000040