Commit 26da4abf authored by Kajol Jain's avatar Kajol Jain Committed by Peter Zijlstra
Browse files

powerpc/perf: Fix data source encodings for L2.1 and L3.1 accesses 



Fix the data source encodings to represent L2.1/L3.1(another core's
L2/L3 on the same node) accesses properly for power10 and older
plaforms.

Add new macros(LEVEL/REM) which can be used to add mem_lvl_num and remote
field data inside perf_mem_data_src structure.

Result in power9 system with patch changes:

localhost:~/linux/tools/perf # ./perf mem report | grep Remote
     0.01%             1  252           Remote core, same node L3 or L3 hit  [.] 0x0000000000002dd0                producer_consumer   [.] 0x00007fff7f25eb90
anon               HitM          N/A                     No       N/A        0              0
     0.01%             1  220           Remote core, same node L3 or L3 hit  [.] 0x0000000000002dd0                producer_consumer   [.] 0x00007fff77776d90
anon               HitM          N/A                     No       N/A        0              0
     0.01%             1  220           Remote core, same node L3 or L3 hit  [.] 0x0000000000002dd0                producer_consumer   [.] 0x00007fff817d9410
anon               HitM          N/A                     No       N/A        0              0

Fixes: 79e96f8f ("powerpc/perf: Export memory hierarchy info to user space")
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20211006140654.298352-5-kjain@linux.ibm.com
parent cae1d759

arch/powerpc/perf/isa207-common.c

+21 −5
Original line number Diff line number Diff line
@@ -238,11 +238,27 @@ static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 
		ret |= P(SNOOP, HIT);

		break;

	case 5:

		ret = PH(LVL, REM_CCE1);

		if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))

			ret |= P(SNOOP, HIT);

		else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))

			ret |= P(SNOOP, HITM);

		if (cpu_has_feature(CPU_FTR_ARCH_31)) {

			ret = REM | P(HOPS, 0);



			if (sub_idx == 0 || sub_idx == 4)

				ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);

			else if (sub_idx == 1 || sub_idx == 5)

				ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);

			else if (sub_idx == 2 || sub_idx == 6)

				ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);

			else if (sub_idx == 3 || sub_idx == 7)

				ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);

		} else {

			if (sub_idx == 0)

				ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);

			else if (sub_idx == 1)

				ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);

			else if (sub_idx == 2 || sub_idx == 4)

				ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0);

			else if (sub_idx == 3 || sub_idx == 5)

				ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0);

		}

		break;

	case 6:

		ret = PH(LVL, REM_CCE2);

arch/powerpc/perf/isa207-common.h

+2 −0
Original line number Diff line number Diff line
@@ -273,6 +273,8 @@ 
#define P(a, b)				PERF_MEM_S(a, b)

#define PH(a, b)			(P(LVL, HIT) | P(a, b))

#define PM(a, b)			(P(LVL, MISS) | P(a, b))

#define LEVEL(x)			P(LVLNUM, x)

#define REM				P(REMOTE, REMOTE)



int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1);

int isa207_compute_mmcr(u64 event[], int n_ev,