Commit 26d2e042 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'macb-fixed-link-fixes' 



Robert Hancock says:

====================
macb SGMII fixed-link fixes

Some fixes to the macb driver for use in SGMII mode with a fixed-link (such as
for chip-to-chip connectivity).
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c232f81b e276e5e4

drivers/net/ethernet/cadence/macb.h

+14 −0
Original line number Diff line number Diff line
@@ -159,6 +159,16 @@ 
#define GEM_PEFTN		0x01f4 /* PTP Peer Event Frame Tx Ns */

#define GEM_PEFRSL		0x01f8 /* PTP Peer Event Frame Rx Sec Low */

#define GEM_PEFRN		0x01fc /* PTP Peer Event Frame Rx Ns */

#define GEM_PCSCNTRL		0x0200 /* PCS Control */

#define GEM_PCSSTS		0x0204 /* PCS Status */

#define GEM_PCSPHYTOPID		0x0208 /* PCS PHY Top ID */

#define GEM_PCSPHYBOTID		0x020c /* PCS PHY Bottom ID */

#define GEM_PCSANADV		0x0210 /* PCS AN Advertisement */

#define GEM_PCSANLPBASE		0x0214 /* PCS AN Link Partner Base */

#define GEM_PCSANEXP		0x0218 /* PCS AN Expansion */

#define GEM_PCSANNPTX		0x021c /* PCS AN Next Page TX */

#define GEM_PCSANNPLP		0x0220 /* PCS AN Next Page LP */

#define GEM_PCSANEXTSTS		0x023c /* PCS AN Extended Status */

#define GEM_DCFG1		0x0280 /* Design Config 1 */

#define GEM_DCFG2		0x0284 /* Design Config 2 */

#define GEM_DCFG3		0x0288 /* Design Config 3 */
@@ -478,6 +488,10 @@ 
#define GEM_HS_MAC_SPEED_OFFSET			0

#define GEM_HS_MAC_SPEED_SIZE			3



/* Bitfields in PCSCNTRL */

#define GEM_PCSAUTONEG_OFFSET			12

#define GEM_PCSAUTONEG_SIZE			1



/* Bitfields in DCFG1. */

#define GEM_IRQCOR_OFFSET			23

#define GEM_IRQCOR_SIZE				1

drivers/net/ethernet/cadence/macb_main.c

+30 −0
Original line number Diff line number Diff line
@@ -694,6 +694,22 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode, 
	if (old_ncr ^ ncr)

		macb_or_gem_writel(bp, NCR, ncr);



	/* Disable AN for SGMII fixed link configuration, enable otherwise.

	 * Must be written after PCSSEL is set in NCFGR,

	 * otherwise writes will not take effect.

	 */

	if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {

		u32 pcsctrl, old_pcsctrl;



		old_pcsctrl = gem_readl(bp, PCSCNTRL);

		if (mode == MLO_AN_FIXED)

			pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);

		else

			pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);

		if (old_pcsctrl != pcsctrl)

			gem_writel(bp, PCSCNTRL, pcsctrl);

	}



	spin_unlock_irqrestore(&bp->lock, flags);

}
@@ -847,6 +863,15 @@ static int macb_phylink_connect(struct macb *bp) 
	return 0;

}



static void macb_get_pcs_fixed_state(struct phylink_config *config,

				     struct phylink_link_state *state)

{

	struct net_device *ndev = to_net_dev(config->dev);

	struct macb *bp = netdev_priv(ndev);



	state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;

}



/* based on au1000_eth. c*/

static int macb_mii_probe(struct net_device *dev)

{
@@ -855,6 +880,11 @@ static int macb_mii_probe(struct net_device *dev) 
	bp->phylink_config.dev = &dev->dev;

	bp->phylink_config.type = PHYLINK_NETDEV;



	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {

		bp->phylink_config.poll_fixed_state = true;

		bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;

	}



	bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,

				     bp->phy_interface, &macb_phylink_ops);

	if (IS_ERR(bp->phylink)) {