Commit 26aae8cc authored by Andrew Cooper's avatar Andrew Cooper Committed by Borislav Petkov
Browse files

x86/cpu/amd: Enumerate BTC_NO 



BTC_NO indicates that hardware is not susceptible to Branch Type Confusion.

Zen3 CPUs don't suffer BTC.

Hypervisors are expected to synthesise BTC_NO when it is appropriate
given the migration pool, to prevent kernels using heuristics.

  [ bp: Massage. ]

Signed-off-by: default avatarAndrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 7a05bc95

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -322,6 +322,7 @@ 
#define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */

#define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */

#define X86_FEATURE_CPPC		(13*32+27) /* Collaborative Processor Performance Control */

#define X86_FEATURE_BTC_NO		(13*32+29) /* "" Not vulnerable to Branch Type Confusion */

#define X86_FEATURE_BRS			(13*32+31) /* Branch Sampling available */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

arch/x86/kernel/cpu/amd.c

+15 −6
Original line number Diff line number Diff line
@@ -890,12 +890,21 @@ static void init_amd_zn(struct cpuinfo_x86 *c) 
	node_reclaim_distance = 32;

#endif



	/* Fix up CPUID bits, but only if not virtualised. */

	if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {



		/* Erratum 1076: CPB feature bit not being set in CPUID. */

		if (!cpu_has(c, X86_FEATURE_CPB))

			set_cpu_cap(c, X86_FEATURE_CPB);



		/*

	 * Fix erratum 1076: CPB feature bit not being set in CPUID.

	 * Always set it, except when running under a hypervisor.

		 * Zen3 (Fam19 model < 0x10) parts are not susceptible to

		 * Branch Type Confusion, but predate the allocation of the

		 * BTC_NO bit.

		 */

	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))

		set_cpu_cap(c, X86_FEATURE_CPB);

		if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))

			set_cpu_cap(c, X86_FEATURE_BTC_NO);

	}

}



static void init_amd(struct cpuinfo_x86 *c)

arch/x86/kernel/cpu/common.c

+4 −2
Original line number Diff line number Diff line
@@ -1359,8 +1359,10 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
	    !arch_cap_mmio_immune(ia32_cap))

		setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);



	if ((cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)))

	if (!cpu_has(c, X86_FEATURE_BTC_NO)) {

		if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))

			setup_force_cpu_bug(X86_BUG_RETBLEED);

	}



	if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))

		return;