Loading drivers/i2c/busses/i2c-tegra.c +19 −16 Original line number Diff line number Diff line Loading @@ -669,10 +669,11 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); if (in_interrupt()) err = readl_poll_timeout_atomic(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); 1000, I2C_CONFIG_LOAD_TIMEOUT); else err = readl_poll_timeout(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); err = readl_poll_timeout(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); if (err) { dev_warn(i2c_dev->dev, Loading Loading @@ -1013,7 +1014,8 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) } static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *msg, enum msg_end_type end_state) struct i2c_msg *msg, enum msg_end_type end_state) { u32 packet_header; u32 int_mask; Loading Loading @@ -1150,8 +1152,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (err) return err; time_left = wait_for_completion_timeout( &i2c_dev->dma_complete, time_left = wait_for_completion_timeout(&i2c_dev->dma_complete, msecs_to_jiffies(xfer_time)); if (time_left == 0) { dev_err(i2c_dev->dev, "DMA transfer timeout\n"); Loading Loading @@ -1260,14 +1261,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { struct device_node *np = i2c_dev->dev->of_node; int ret; bool multi_mode; ret = of_property_read_u32(np, "clock-frequency", &i2c_dev->bus_clk_rate); if (ret) i2c_dev->bus_clk_rate = 100000; /* default clock rate */ i2c_dev->is_multimaster_mode = of_property_read_bool(np, "multi-master"); multi_mode = of_property_read_bool(np, "multi-master"); i2c_dev->is_multimaster_mode = multi_mode; } static const struct i2c_algorithm tegra_i2c_algo = { Loading Loading @@ -1680,6 +1682,7 @@ static const struct dev_pm_ops tegra_i2c_pm = { SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, NULL) }; #define TEGRA_I2C_PM (&tegra_i2c_pm) #else #define TEGRA_I2C_PM NULL Loading Loading
drivers/i2c/busses/i2c-tegra.c +19 −16 Original line number Diff line number Diff line Loading @@ -669,10 +669,11 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); if (in_interrupt()) err = readl_poll_timeout_atomic(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); 1000, I2C_CONFIG_LOAD_TIMEOUT); else err = readl_poll_timeout(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); err = readl_poll_timeout(addr, val, val == 0, 1000, I2C_CONFIG_LOAD_TIMEOUT); if (err) { dev_warn(i2c_dev->dev, Loading Loading @@ -1013,7 +1014,8 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) } static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *msg, enum msg_end_type end_state) struct i2c_msg *msg, enum msg_end_type end_state) { u32 packet_header; u32 int_mask; Loading Loading @@ -1150,8 +1152,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (err) return err; time_left = wait_for_completion_timeout( &i2c_dev->dma_complete, time_left = wait_for_completion_timeout(&i2c_dev->dma_complete, msecs_to_jiffies(xfer_time)); if (time_left == 0) { dev_err(i2c_dev->dev, "DMA transfer timeout\n"); Loading Loading @@ -1260,14 +1261,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { struct device_node *np = i2c_dev->dev->of_node; int ret; bool multi_mode; ret = of_property_read_u32(np, "clock-frequency", &i2c_dev->bus_clk_rate); if (ret) i2c_dev->bus_clk_rate = 100000; /* default clock rate */ i2c_dev->is_multimaster_mode = of_property_read_bool(np, "multi-master"); multi_mode = of_property_read_bool(np, "multi-master"); i2c_dev->is_multimaster_mode = multi_mode; } static const struct i2c_algorithm tegra_i2c_algo = { Loading Loading @@ -1680,6 +1682,7 @@ static const struct dev_pm_ops tegra_i2c_pm = { SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, NULL) }; #define TEGRA_I2C_PM (&tegra_i2c_pm) #else #define TEGRA_I2C_PM NULL Loading