Commit 268c67e5 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move ppgtt_type and ppgtt_size to runtime info 



If it's modified runtime, it's runtime info.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMaarten Lankhort <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9a9b94cb79a00229da5a564a16ea750a6d392ab6.1660910433.git.jani.nikula@intel.com
parent 9d0bad17

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

+2 −2
Original line number Diff line number Diff line
@@ -1764,8 +1764,8 @@ int i915_gem_huge_page_mock_selftests(void) 
		return -ENOMEM;



	/* Pretend to be a device which supports the 48b PPGTT */

	mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;

	mkwrite_device_info(dev_priv)->ppgtt_size = 48;

	RUNTIME_INFO(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;

	RUNTIME_INFO(dev_priv)->ppgtt_size = 48;



	ppgtt = i915_ppgtt_create(to_gt(dev_priv), 0);

	if (IS_ERR(ppgtt)) {

drivers/gpu/drm/i915/gt/intel_ppgtt.c

+1 −1
Original line number Diff line number Diff line
@@ -308,7 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 
	ppgtt->vm.gt = gt;

	ppgtt->vm.i915 = i915;

	ppgtt->vm.dma = i915->drm.dev;

	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);

	ppgtt->vm.total = BIT_ULL(RUNTIME_INFO(i915)->ppgtt_size);

	ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;



	dma_resv_init(&ppgtt->vm._resv);

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1210,7 +1210,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 


#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)



#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)

#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)

#define HAS_PPGTT(dev_priv) \

	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)

#define HAS_FULL_PPGTT(dev_priv) \

drivers/gpu/drm/i915/i915_pci.c

+18 −18
Original line number Diff line number Diff line
@@ -421,8 +421,8 @@ static const struct intel_device_info ilk_m_info = { 
	.has_rc6p = 1, \

	.has_rps = true, \

	.dma_mask_size = 40, \

	.ppgtt_type = INTEL_PPGTT_ALIASING, \

	.ppgtt_size = 31, \

	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \

	.__runtime.ppgtt_size = 31, \

	I9XX_PIPE_OFFSETS, \

	I9XX_CURSOR_OFFSETS, \

	ILK_COLORS, \
@@ -474,8 +474,8 @@ static const struct intel_device_info snb_m_gt2_info = { 
	.has_reset_engine = true, \

	.has_rps = true, \

	.dma_mask_size = 40, \

	.ppgtt_type = INTEL_PPGTT_ALIASING, \

	.ppgtt_size = 31, \

	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \

	.__runtime.ppgtt_size = 31, \

	IVB_PIPE_OFFSETS, \

	IVB_CURSOR_OFFSETS, \

	IVB_COLORS, \
@@ -535,8 +535,8 @@ static const struct intel_device_info vlv_info = { 
	.display.has_gmch = 1,

	.display.has_hotplug = 1,

	.dma_mask_size = 40,

	.ppgtt_type = INTEL_PPGTT_ALIASING,

	.ppgtt_size = 31,

	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,

	.__runtime.ppgtt_size = 31,

	.has_snoop = true,

	.has_coherent_ggtt = false,

	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
@@ -585,8 +585,8 @@ static const struct intel_device_info hsw_gt3_info = { 
	GEN(8), \

	.has_logical_ring_contexts = 1, \

	.dma_mask_size = 39, \

	.ppgtt_type = INTEL_PPGTT_FULL, \

	.ppgtt_size = 48, \

	.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \

	.__runtime.ppgtt_size = 48, \

	.has_64bit_reloc = 1



#define BDW_PLATFORM \
@@ -633,8 +633,8 @@ static const struct intel_device_info chv_info = { 
	.has_logical_ring_contexts = 1,

	.display.has_gmch = 1,

	.dma_mask_size = 39,

	.ppgtt_type = INTEL_PPGTT_FULL,

	.ppgtt_size = 32,

	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,

	.__runtime.ppgtt_size = 32,

	.has_reset_engine = 1,

	.has_snoop = true,

	.has_coherent_ggtt = false,
@@ -719,8 +719,8 @@ static const struct intel_device_info skl_gt4_info = { 
	.has_logical_ring_contexts = 1, \

	.has_gt_uc = 1, \

	.dma_mask_size = 39, \

	.ppgtt_type = INTEL_PPGTT_FULL, \

	.ppgtt_size = 48, \

	.__runtime.ppgtt_type = INTEL_PPGTT_FULL, \

	.__runtime.ppgtt_size = 48, \

	.has_reset_engine = 1, \

	.has_snoop = true, \

	.has_coherent_ggtt = false, \
@@ -848,14 +848,14 @@ static const struct intel_device_info ehl_info = { 
	GEN11_FEATURES,

	PLATFORM(INTEL_ELKHARTLAKE),

	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

	.ppgtt_size = 36,

	.__runtime.ppgtt_size = 36,

};



static const struct intel_device_info jsl_info = {

	GEN11_FEATURES,

	PLATFORM(INTEL_JASPERLAKE),

	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

	.ppgtt_size = 36,

	.__runtime.ppgtt_size = 36,

};



#define GEN12_FEATURES \
@@ -927,7 +927,7 @@ static const struct intel_device_info dg1_info = { 
		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |

		BIT(VCS0) | BIT(VCS2),

	/* Wa_16011227922 */

	.ppgtt_size = 47,

	.__runtime.ppgtt_size = 47,

};



static const struct intel_device_info adl_s_info = {
@@ -994,7 +994,7 @@ static const struct intel_device_info adl_p_info = { 
	.display.has_psr_hw_tracking = 0,

	.platform_engine_mask =

		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

	.ppgtt_size = 48,

	.__runtime.ppgtt_size = 48,

	.dma_mask_size = 39,

};
@@ -1023,8 +1023,8 @@ static const struct intel_device_info adl_p_info = { 
	.has_reset_engine = 1, \

	.has_rps = 1, \

	.has_runtime_pm = 1, \

	.ppgtt_size = 48, \

	.ppgtt_type = INTEL_PPGTT_FULL

	.__runtime.ppgtt_size = 48, \

	.__runtime.ppgtt_type = INTEL_PPGTT_FULL



#define XE_HPM_FEATURES \

	.media.ver = 12, \

drivers/gpu/drm/i915/intel_device_info.c

+3 −3
Original line number Diff line number Diff line
@@ -112,8 +112,8 @@ void intel_device_info_print(const struct intel_device_info *info, 
	drm_printf(p, "memory-regions: %x\n", info->memory_regions);

	drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);

	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));

	drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);

	drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);

	drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);

	drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);

	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);



#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {

		drm_info(&dev_priv->drm,

			 "Disabling ppGTT for VT-d support\n");

		info->ppgtt_type = INTEL_PPGTT_NONE;

		runtime->ppgtt_type = INTEL_PPGTT_NONE;

	}



	runtime->rawclk_freq = intel_read_rawclk(dev_priv);