Commit 2641c7b7 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: use low clocks for no plane configs 



Stream only configurations do not require DCFCLK, SOCCLK, DPPCLK
or FCLK. They also always allow pstate change.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e4c1b01b

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+14 −4
Original line number Diff line number Diff line
@@ -483,7 +483,7 @@ void dcn31_calculate_wm_and_dlg_fp( 
		int pipe_cnt,

		int vlevel)

{

	int i, pipe_idx, active_dpp_count = 0;

	int i, pipe_idx, active_hubp_count = 0;

	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];



	dc_assert_fp_enabled();
@@ -529,7 +529,7 @@ void dcn31_calculate_wm_and_dlg_fp( 
			continue;



		if (context->res_ctx.pipe_ctx[i].plane_state)

			active_dpp_count++;

			active_hubp_count++;



		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
@@ -547,9 +547,19 @@ void dcn31_calculate_wm_and_dlg_fp( 
	}



	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

	/* For 31x apu pstate change is only supported if possible in vactive or if there are no active dpps */

	/* For 31x apu pstate change is only supported if possible in vactive*/

	context->bw_ctx.bw.dcn.clk.p_state_change_support =

			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive || !active_dpp_count;

			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive;

	/* If DCN isn't making memory requests we can allow pstate change and lower clocks */

	if (!active_hubp_count) {

		context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

		context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

	}

}



void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+13 −1
Original line number Diff line number Diff line
@@ -1228,7 +1228,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 
				       display_e2e_pipe_params_st *pipes,

				       int pipe_cnt, int vlevel)

{

	int i, pipe_idx;

	int i, pipe_idx, active_hubp_count = 0;

	bool usr_retraining_support = false;

	bool unbounded_req_enabled = false;
@@ -1273,6 +1273,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 
	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		if (context->res_ctx.pipe_ctx[i].plane_state)

			active_hubp_count++;

		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,

				pipe_idx);

		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
@@ -1298,6 +1300,16 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, 
		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

		pipe_idx++;

	}

	/* If DCN isn't making memory requests we can allow pstate change and lower clocks */

	if (!active_hubp_count) {

		context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

		context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

	}

	/*save a original dppclock copy*/

	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;