Commit 2625ad19 authored by Wang ShaoBo's avatar Wang ShaoBo Committed by Zheng Zengkai
Browse files

arm64/mpam: Add hook-events id for ctrl features 



hulk inclusion
category: feature
feature: ARM MPAM support
bugzilla: 48265
CVE: NA

--------------------------------

Reading/Writing registers directly for getting or putting configuration
is not friendly with expansion and legibility, multiple types of schemata
ctrls is supported, of which value should be converted to a proper value
based on specific definition and range in corresponding register according
to MPAM spec, Using event id instead to indicate which type configuration
we want to get looks easier for us.

Besides, different hook-events have different setting bound such as bwa_wd
for adaptive range conversion when writing configuration, this can be
associated with specific event for conversion.

Signed-off-by: default avatarWang ShaoBo <bobo.shaobowang@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: default avatarCheng Jian <cj.chengjian@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 25f05a7e

arch/arm64/include/asm/mpam.h

+1 −1
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ struct raw_resctrl_resource { 


	int			data_width;

	const char		*format_str;

	int (*parse_ctrlval)(char *buf, struct raw_resctrl_resource *r,

	int (*parse_ctrlval)(char *buf, struct resctrl_resource *r,

				struct resctrl_staged_config *cfg,

				enum resctrl_ctrl_type ctrl_type);

arch/arm64/include/asm/mpam_resource.h

+8 −9
Original line number Diff line number Diff line
@@ -69,18 +69,17 @@ 
#define CPBM_WD_MASK        0xFFFF

#define CPBM_MASK           0x7FFF



#define BWA_WD              6		/* hard code for P680 */

#define MBW_MAX_MASK        0xFC00

#define MBW_MAX_HARDLIM             BIT(31)

#define MBW_PROP_HARDLIM            BIT(31)

#define MBW_MAX_MASK                GENMASK(15, 0)

#define MBW_MAX_BWA_FRACT(w)        GENMASK(w - 1, 0)

#define MBW_MAX_SET(v)      (MBW_MAX_HARDLIM|((v) << (16 - BWA_WD)))

#define MBW_MAX_GET(v)      (((v) & MBW_MAX_MASK) >> (16 - BWA_WD))

#define MBW_MAX_SET_HDL(r)          (r | MBW_MAX_HARDLIM)

#define MBW_MAX_GET_HDL(r)          (r & MBW_MAX_HARDLIM)

#define MBW_MAX_SET(v, w)           (v << (16 - w))

/* MPAMCFG_MBW_PROP */

#define MBW_PROP_HARDLIM            BIT(31)

#define MBW_PROP_SET_HDL(r)   (r | MBW_PROP_HARDLIM)

/* MPAMCFG_MBW_MAX */

#define MBW_MAX_SET_HDL(r)    (r | MBW_MAX_HARDLIM)

#define MBW_MAX_GET_HDL(r)    ((r & MBW_MAX_HARDLIM) >> 31)

#define MBW_MAX_GET(v, w)     (((v) & MBW_MAX_MASK) >> (16 - w))



#define MSMON_MATCH_PMG     BIT(17)

#define MSMON_MATCH_PARTID  BIT(16)

arch/arm64/include/asm/resctrl.h

+5 −0
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ enum rdt_event_id { 
	QOS_L3_MBM_TOTAL_EVENT_ID       = 0x02,

	QOS_L3_MBM_LOCAL_EVENT_ID       = 0x03,



	QOS_CAT_CPBM_EVENT_ID           = 0x04,

	QOS_CAT_PRI_EVENT_ID            = 0x05,

	QOS_MBA_MAX_EVENT_ID            = 0x06,

	QOS_MBA_PRI_EVENT_ID            = 0x07,

	QOS_MBA_HDL_EVENT_ID            = 0x08,

	/* Must be the last */

	RESCTRL_NUM_EVENT_IDS,

};

arch/arm64/kernel/mpam/mpam_ctrlmon.c

+1 −1
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ parse_line(char *line, struct resctrl_resource *r, 
	list_for_each_entry(d, &r->domains, list) {

		if (d->id == dom_id) {

			resctrl_cdp_map(clos, closid, conf_type, hw_closid);

			if (rr->parse_ctrlval(dom, rr,

			if (rr->parse_ctrlval(dom, r,

				&d->staged_cfg[conf_type], ctrl_type))

				return -EINVAL;

			d->staged_cfg[conf_type].hw_closid = hw_closid;

arch/arm64/kernel/mpam/mpam_device.c

+44 −6
Original line number Diff line number Diff line
@@ -753,7 +753,7 @@ static void mpam_reset_device_config(struct mpam_component *comp, 
		mpam_reset_device_bitmap(dev, MPAMCFG_MBW_PBM,

				dev->mbw_pbm_bits);

	if (mpam_has_feature(mpam_feat_mbw_max, dev->features)) {

		mbw_max = MBW_MAX_SET(MBW_MAX_BWA_FRACT(dev->bwa_wd));

		mbw_max = MBW_MAX_SET(MBW_MAX_BWA_FRACT(dev->bwa_wd), dev->bwa_wd);

		mbw_max = MBW_MAX_SET_HDL(mbw_max);

		mpam_write_reg(dev, MPAMCFG_MBW_MAX, mbw_max);

	}
@@ -1177,7 +1177,7 @@ mpam_device_config(struct mpam_device *dev, struct sd_closid *closid, 


	if (mpam_has_feature(mpam_feat_mbw_max, dev->features)) {

		if (cfg && mpam_has_feature(mpam_feat_mbw_max, cfg->valid)) {

			mbw_max = MBW_MAX_SET(cfg->mbw_max);

			mbw_max = MBW_MAX_SET(cfg->mbw_max, dev->bwa_wd);

			if (!mpam_has_feature(mpam_feat_part_hdl, cfg->valid) ||

				(mpam_has_feature(mpam_feat_part_hdl, cfg->valid) && cfg->hdl))

				mbw_max = MBW_MAX_SET_HDL(mbw_max);
@@ -1382,14 +1382,15 @@ static void mpam_component_read_mpamcfg(void *_ctx) 
	struct mpam_device_sync *ctx = (struct mpam_device_sync *)_ctx;

	struct mpam_component *comp = ctx->comp;

	struct sync_args *args = ctx->args;

	u64 val;

	u16 reg;

	u64 val = 0;

	u32 partid, intpartid;

	u32 dspri = 0;

	u32 intpri = 0;

	u64 range;



	if (!args)

		return;



	reg = args->reg;



	partid = args->closid.reqpartid;

	intpartid = args->closid.intpartid;
@@ -1407,7 +1408,44 @@ static void mpam_component_read_mpamcfg(void *_ctx) 


		mpam_write_reg(dev, MPAMCFG_PART_SEL, partid);

		wmb();

		val = mpam_read_reg(dev, reg);



		switch (args->eventid) {

		case QOS_CAT_CPBM_EVENT_ID:

			if (!mpam_has_feature(mpam_feat_cpor_part, dev->features))

				break;

			val = mpam_read_reg(dev, MPAMCFG_CPBM);

			break;

		case QOS_MBA_MAX_EVENT_ID:

			if (!mpam_has_feature(mpam_feat_mbw_max, dev->features))

				break;

			val = mpam_read_reg(dev, MPAMCFG_MBW_MAX);

			range = MBW_MAX_BWA_FRACT(dev->bwa_wd);

			val = MBW_MAX_GET(val, dev->bwa_wd) * (MAX_MBA_BW - 1) / range;

			break;

		case QOS_MBA_HDL_EVENT_ID:

			if (!mpam_has_feature(mpam_feat_mbw_max, dev->features))

				break;

			val = mpam_read_reg(dev, MPAMCFG_MBW_MAX);

			val = MBW_MAX_GET_HDL(val);

			break;

		case QOS_CAT_PRI_EVENT_ID:

		case QOS_MBA_PRI_EVENT_ID:

			if (mpam_has_feature(mpam_feat_intpri_part, dev->features))

				intpri = MPAMCFG_INTPRI_GET(val);

			if (mpam_has_feature(mpam_feat_dspri_part, dev->features))

				dspri = MPAMCFG_DSPRI_GET(val);

			if (!mpam_has_feature(mpam_feat_intpri_part_0_low,

				dev->features))

				intpri = GENMASK(dev->intpri_wd - 1, 0) & ~intpri;

			if (!mpam_has_feature(mpam_feat_dspri_part_0_low,

				dev->features))

				dspri = GENMASK(dev->intpri_wd - 1, 0) & ~dspri;

			val = (dspri > intpri) ? dspri : intpri;

			break;

		default:

			break;

		}



		atomic64_add(val, &ctx->cfg_value);

		spin_unlock_irqrestore(&dev->lock, flags);