Commit 25e7976d authored by Andrzej Hajda's avatar Andrzej Hajda
Browse files

drm/i915/mtl: do not enable render power-gating on MTL 

Multiple CI tests fails with forcewake ack timeouts if render
power gating is enabled.
BSpec 52698 states it should be 0 for MTL, but apparently
this info is outdated. Anyway since the patch makes MTL pass basic
tests added FIXME tag informing this is temporary workaround.

v2: added FIXME tag

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983


Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230517-mtl_disable_render_pg-v2-1-0b51180a43f0@intel.com
parent 6f22587c

drivers/gpu/drm/i915/gt/intel_rc6.c

+8 −2
Original line number Diff line number Diff line
@@ -117,8 +117,14 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) 
			GEN6_RC_CTL_RC6_ENABLE |

			GEN6_RC_CTL_EI_MODE(1);



	/* Wa_16011777198 - Render powergating must remain disabled */

	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||

	/*

	 * Wa_16011777198 and BSpec 52698 - Render powergating must be off.

	 * FIXME BSpec is outdated, disabling powergating for MTL is just

	 * temporary wa and should be removed after fixing real cause

	 * of forcewake timeouts.

	 */

	if (IS_METEORLAKE(gt->i915) ||

	    IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||

	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))

		pg_enable =

			GEN9_MEDIA_PG_ENABLE |