Commit 25bba42f authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Vinod Koul
Browse files

phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register 



Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-6-git-send-email-hayashi.kunihiko@socionext.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 1c1597c8

drivers/phy/socionext/phy-uniphier-pcie.c

+5 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define PCL_PHY_R26		26

#define   VCO_CTRL		GENMASK(7, 4)	/* Tx VCO adjustment value */

#define   VCO_CTRL_INIT_VAL	5

#define PCL_PHY_R28		28

#define   VCOPLL_CLMP		GENMASK(3, 2)	/* Tx VCOPLL clamp mode */

#define   VCOPLL_CLMP_VAL	0



struct uniphier_pciephy_priv {

	void __iomem *base;
@@ -158,6 +161,8 @@ static int uniphier_pciephy_init(struct phy *phy) 
				   FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));

	uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,

				   FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));

	uniphier_pciephy_set_param(priv, PCL_PHY_R28, VCOPLL_CLMP,

				   FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));

	usleep_range(1, 10);



	uniphier_pciephy_deassert(priv);