Commit 25b054c3 authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family 



[Why]
Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other
ASICs.

[How]
Add guard to check chip family is yellow carp before applying logic.

Reviewed-by: default avatarHansen Dsouza <hansen.dsouza@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4a37c55b

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+2 −1
Original line number Diff line number Diff line
@@ -84,7 +84,8 @@ static enum phyd32clk_clock_source get_phy_mux_symclk( 
		struct dcn_dccg *dccg_dcn,

		enum phyd32clk_clock_source src)

{

	if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

	if (dccg_dcn->base.ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&

			dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

		if (src == PHYD32CLKC)

			src = PHYD32CLKF;

		if (src == PHYD32CLKD)