Commit 257449c6 authored by Sandipan Das's avatar Sandipan Das Committed by Peter Zijlstra
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x86/cpufeatures: Add LbrExtV2 feature bit 



CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some new performance
monitoring features for AMD processors.

Bit 1 of EAX indicates support for Last Branch Record Extension Version 2
(LbrExtV2) features. If found to be set during PMU initialization, the EBX
bits of the same leaf can be used to determine the number of available LBR
entries.

For better utilization of feature words, LbrExtV2 is added as a scattered
feature bit.

[peterz: Rename to AMD_LBR_V2]
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/172d2b0df39306ed77221c45ee1aa62e8ae0548d.1660211399.git.sandipan.das@amd.com
parent 706460a9

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
#define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

/* FREE!                                ( 3*32+17) */

#define X86_FEATURE_AMD_LBR_V2		( 3*32+17) /* AMD Last Branch Record Extension Version 2 */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },

	{ X86_FEATURE_MBA,		CPUID_EBX,  6, 0x80000008, 0 },

	{ X86_FEATURE_PERFMON_V2,	CPUID_EAX,  0, 0x80000022, 0 },

	{ X86_FEATURE_AMD_LBR_V2,	CPUID_EAX,  1, 0x80000022, 0 },

	{ 0, 0, 0, 0, 0 }

};