Commit 25730d8b authored by Edward Cree's avatar Edward Cree Committed by David S. Miller
Browse files

sfc: add extra RX channel to receive MAE counter updates on ef100 



Currently there is no counter-allocating machinery to connect the
 resulting counter update values to; that will be added in a
 subsequent patch.

Signed-off-by: default avatarEdward Cree <ecree.xilinx@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e5731274

drivers/net/ethernet/sfc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ sfc-y += efx.o efx_common.o efx_channels.o nic.o \ 
			   ef100_ethtool.o ef100_rx.o ef100_tx.o

sfc-$(CONFIG_SFC_MTD)	+= mtd.o

sfc-$(CONFIG_SFC_SRIOV)	+= sriov.o ef10_sriov.o ef100_sriov.o ef100_rep.o \

                           mae.o tc.o tc_bindings.o

                           mae.o tc.o tc_bindings.o tc_counters.o



obj-$(CONFIG_SFC)	+= sfc.o

drivers/net/ethernet/sfc/mae_counter_format.h

0 → 100644
+73 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/****************************************************************************

 * Driver for Solarflare network controllers and boards

 * Copyright 2020 Xilinx, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation, incorporated herein by reference.

 */



/* Format of counter packets (version 2) from the ef100 Match-Action Engine */



#ifndef EFX_MAE_COUNTER_FORMAT_H

#define EFX_MAE_COUNTER_FORMAT_H





/*------------------------------------------------------------*/

/*

 * ER_RX_SL_PACKETISER_HEADER_WORD(160bit):

 * 

 */

#define ER_RX_SL_PACKETISER_HEADER_WORD_SIZE 20

#define ER_RX_SL_PACKETISER_HEADER_WORD_WIDTH 160



#define ERF_SC_PACKETISER_HEADER_VERSION_LBN 0

#define ERF_SC_PACKETISER_HEADER_VERSION_WIDTH 8

#define ERF_SC_PACKETISER_HEADER_VERSION_VALUE 2

#define ERF_SC_PACKETISER_HEADER_IDENTIFIER_LBN 8

#define ERF_SC_PACKETISER_HEADER_IDENTIFIER_WIDTH 8

#define ERF_SC_PACKETISER_HEADER_IDENTIFIER_AR 0

#define ERF_SC_PACKETISER_HEADER_IDENTIFIER_CT 1

#define ERF_SC_PACKETISER_HEADER_IDENTIFIER_OR 2

#define ERF_SC_PACKETISER_HEADER_HEADER_OFFSET_LBN 16

#define ERF_SC_PACKETISER_HEADER_HEADER_OFFSET_WIDTH 8

#define ERF_SC_PACKETISER_HEADER_HEADER_OFFSET_DEFAULT 0x4

#define ERF_SC_PACKETISER_HEADER_PAYLOAD_OFFSET_LBN 24

#define ERF_SC_PACKETISER_HEADER_PAYLOAD_OFFSET_WIDTH 8

#define ERF_SC_PACKETISER_HEADER_PAYLOAD_OFFSET_DEFAULT 0x14

#define ERF_SC_PACKETISER_HEADER_INDEX_LBN 32

#define ERF_SC_PACKETISER_HEADER_INDEX_WIDTH 16

#define ERF_SC_PACKETISER_HEADER_COUNT_LBN 48

#define ERF_SC_PACKETISER_HEADER_COUNT_WIDTH 16

#define ERF_SC_PACKETISER_HEADER_RESERVED_0_LBN 64

#define ERF_SC_PACKETISER_HEADER_RESERVED_0_WIDTH 32

#define ERF_SC_PACKETISER_HEADER_RESERVED_1_LBN 96

#define ERF_SC_PACKETISER_HEADER_RESERVED_1_WIDTH 32

#define ERF_SC_PACKETISER_HEADER_RESERVED_2_LBN 128

#define ERF_SC_PACKETISER_HEADER_RESERVED_2_WIDTH 32





/*------------------------------------------------------------*/

/*

 * ER_RX_SL_PACKETISER_PAYLOAD_WORD(128bit):

 * 

 */

#define ER_RX_SL_PACKETISER_PAYLOAD_WORD_SIZE 16

#define ER_RX_SL_PACKETISER_PAYLOAD_WORD_WIDTH 128



#define ERF_SC_PACKETISER_PAYLOAD_COUNTER_INDEX_LBN 0

#define ERF_SC_PACKETISER_PAYLOAD_COUNTER_INDEX_WIDTH 24

#define ERF_SC_PACKETISER_PAYLOAD_RESERVED_LBN 24

#define ERF_SC_PACKETISER_PAYLOAD_RESERVED_WIDTH 8

#define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_OFST 4

#define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_SIZE 6

#define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_LBN 32

#define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_WIDTH 48

#define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_OFST 10

#define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_SIZE 6

#define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_LBN 80

#define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_WIDTH 48





#endif /* EFX_MAE_COUNTER_FORMAT_H */

drivers/net/ethernet/sfc/net_driver.h

+2 −1
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ 
#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS

#define EFX_EXTRA_CHANNEL_IOV	0

#define EFX_EXTRA_CHANNEL_PTP	1

#define EFX_MAX_EXTRA_CHANNELS	2U

#define EFX_EXTRA_CHANNEL_TC	2

#define EFX_MAX_EXTRA_CHANNELS	3U



/* Checksum generation is a per-queue option in hardware, so each

 * queue visible to the networking core is backed by two hardware TX

drivers/net/ethernet/sfc/tc.c

+1 −0
Original line number Diff line number Diff line
@@ -761,6 +761,7 @@ int efx_init_struct_tc(struct efx_nic *efx) 
	efx->tc->dflt.pf.fw_id = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL;

	INIT_LIST_HEAD(&efx->tc->dflt.wire.acts.list);

	efx->tc->dflt.wire.fw_id = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL;

	efx->extra_channel_type[EFX_EXTRA_CHANNEL_TC] = &efx_tc_channel_type;

	return 0;

fail_match_action_ht:

	mutex_destroy(&efx->tc->mutex);

drivers/net/ethernet/sfc/tc.h

+1 −8
Original line number Diff line number Diff line
@@ -14,14 +14,7 @@ 
#include <net/flow_offload.h>

#include <linux/rhashtable.h>

#include "net_driver.h"

#include "mcdi_pcol.h" /* for MAE_COUNTER_TYPE_* */



enum efx_tc_counter_type {

	EFX_TC_COUNTER_TYPE_AR = MAE_COUNTER_TYPE_AR,

	EFX_TC_COUNTER_TYPE_CT = MAE_COUNTER_TYPE_CT,

	EFX_TC_COUNTER_TYPE_OR = MAE_COUNTER_TYPE_OR,

	EFX_TC_COUNTER_TYPE_MAX

};

#include "tc_counters.h"



#define IS_ALL_ONES(v)	(!(typeof (v))~(v))