Commit 256f79d1 authored by Aya Levin's avatar Aya Levin Committed by Saeed Mahameed
Browse files

net/mlx5e: Fix HW TS with CQE compression according to profile 



When the driver's profile doesn't support a dedicated PTP-RQ, the PTP
accuracy of HW TS is affected by the CQE compression. In this case,
turn off CQE compression. Otherwise, the driver crashes:

BUG: kernel NULL pointer dereference, address:0000000000000018
...
...
RIP: 0010:mlx5e_ptp_rx_set_fs+0x25/0x1a0 [mlx5_core]
...
...
Call Trace:
 mlx5e_ptp_activate_channel+0xb2/0xf0 [mlx5_core]
 mlx5e_activate_priv_channels+0x3b9/0x8c0 [mlx5_core]
 ? __mutex_unlock_slowpath+0x45/0x2a0
 ? mlx5e_refresh_tirs+0x151/0x1e0 [mlx5_core]
 mlx5e_switch_priv_channels+0x1cd/0x2d0 [mlx5_core]
 ? mlx5e_xdp_allowed+0x150/0x150 [mlx5_core]
 mlx5e_safe_switch_params+0x118/0x3c0 [mlx5_core]
 ? __mutex_lock+0x6e/0x8e0
 ? mlx5e_hwstamp_set+0xa9/0x300 [mlx5_core]
 mlx5e_hwstamp_set+0x194/0x300 [mlx5_core]
 ? dev_ioctl+0x9b/0x3d0
 mlx5i_ioctl+0x37/0x60 [mlx5_core]
 mlx5i_pkey_ioctl+0x12/0x20 [mlx5_core]
 dev_ioctl+0xa9/0x3d0
 sock_ioctl+0x268/0x420
 __x64_sys_ioctl+0x3d8/0x790
 ? lockdep_hardirqs_on_prepare+0xe4/0x190
 do_syscall_64+0x2d/0x40
entry_SYSCALL_64_after_hwframe+0x44/0xae

Fixes: 960fbfe2 ("net/mlx5e: Allow coexistence of CQE compression and HW TS PTP")
Signed-off-by: default avatarAya Levin <ayal@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@nvidia.com>
Reviewed-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 2a2c84fa

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+52 −15
Original line number Diff line number Diff line
@@ -3984,11 +3984,45 @@ int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) 
	return mlx5e_ptp_rx_manage_fs(priv, set);

}



int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)

static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)

{

	bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;

	int err;



	if (!rx_filter)

		/* Reset CQE compression to Admin default */

		return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);



	if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))

		return 0;



	/* Disable CQE compression */

	netdev_warn(priv->netdev, "Disabling RX cqe compression\n");

	err = mlx5e_modify_rx_cqe_compression_locked(priv, false);

	if (err)

		netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);



	return err;

}



static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)

{

	struct mlx5e_params new_params;



	if (ptp_rx == priv->channels.params.ptp_rx)

		return 0;



	new_params = priv->channels.params;

	new_params.ptp_rx = ptp_rx;

	return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,

					&new_params.ptp_rx, true);

}



int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)

{

	struct hwtstamp_config config;

	bool rx_cqe_compress_def;

	bool ptp_rx;

	int err;



	if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
@@ -4008,13 +4042,12 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 
	}



	mutex_lock(&priv->state_lock);

	new_params = priv->channels.params;

	rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;



	/* RX HW timestamp */

	switch (config.rx_filter) {

	case HWTSTAMP_FILTER_NONE:

		new_params.ptp_rx = false;

		ptp_rx = false;

		break;

	case HWTSTAMP_FILTER_ALL:

	case HWTSTAMP_FILTER_SOME:
@@ -4031,24 +4064,25 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 
	case HWTSTAMP_FILTER_PTP_V2_SYNC:

	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:

	case HWTSTAMP_FILTER_NTP_ALL:

		new_params.ptp_rx = rx_cqe_compress_def;

		config.rx_filter = HWTSTAMP_FILTER_ALL;

		/* ptp_rx is set if both HW TS is set and CQE

		 * compression is set

		 */

		ptp_rx = rx_cqe_compress_def;

		break;

	default:

		mutex_unlock(&priv->state_lock);

		return -ERANGE;

		err = -ERANGE;

		goto err_unlock;

	}



	if (new_params.ptp_rx == priv->channels.params.ptp_rx)

		goto out;

	if (!priv->profile->rx_ptp_support)

		err = mlx5e_hwstamp_config_no_ptp_rx(priv,

						     config.rx_filter != HWTSTAMP_FILTER_NONE);

	else

		err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);

	if (err)

		goto err_unlock;



	err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,

				       &new_params.ptp_rx, true);

	if (err) {

		mutex_unlock(&priv->state_lock);

		return err;

	}

out:

	memcpy(&priv->tstamp, &config, sizeof(config));

	mutex_unlock(&priv->state_lock);
@@ -4057,6 +4091,9 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 


	return copy_to_user(ifr->ifr_data, &config,

			    sizeof(config)) ? -EFAULT : 0;

err_unlock:

	mutex_unlock(&priv->state_lock);

	return err;

}



int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)