Commit 255385ca authored by Dikshita Agarwal's avatar Dikshita Agarwal Committed by Mauro Carvalho Chehab
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media: venus: hfi: Add a 6xx boot logic 



This patch adds a 6xx specific boot logic. The goal is to share as much
code as possible between 3xx, 4xx and 6xx silicon.

We need to do a different write to WRAPPER_INTR_MASK with an additional
write to CPU_CS_H2XSOFTINTEN_V6 and CPU_CS_X2RPMh_V6.

The other writes are the same for 6xx and non-6xx silicon albeit at
different absolute relative locations to the base of the venus address
space.

Signed-off-by: default avatarDikshita Agarwal <dikshita@codeaurora.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 3f9acde8

drivers/media/platform/qcom/venus/hfi_venus.c

+12 −2
Original line number Diff line number Diff line
@@ -442,14 +442,21 @@ static int venus_boot_core(struct venus_hfi_device *hdev) 
{

	struct device *dev = hdev->core->dev;

	static const unsigned int max_tries = 100;

	u32 ctrl_status = 0;

	u32 ctrl_status = 0, mask_val;

	unsigned int count = 0;

	void __iomem *cpu_cs_base = hdev->core->cpu_cs_base;

	void __iomem *wrapper_base = hdev->core->wrapper_base;

	int ret = 0;



	writel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT);

	writel(WRAPPER_INTR_MASK_A2HVCODEC_MASK, wrapper_base + WRAPPER_INTR_MASK);

	if (IS_V6(hdev->core)) {

		mask_val = readl(wrapper_base + WRAPPER_INTR_MASK);

		mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 |

			      WRAPPER_INTR_MASK_A2HCPU_MASK);

	} else {

		mask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK;

	}

	writel(mask_val, wrapper_base + WRAPPER_INTR_MASK);

	writel(1, cpu_cs_base + CPU_CS_SCIACMDARG3);



	while (!ctrl_status && count < max_tries) {
@@ -467,6 +474,9 @@ static int venus_boot_core(struct venus_hfi_device *hdev) 
	if (count >= max_tries)

		ret = -ETIMEDOUT;



	if (IS_V6(hdev->core))

		writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6);



	return ret;

}