Unverified Commit 2524257b authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

dt-bindings: Fix phandle-array issues in the idle-states bindings 



As per 39bd2b6a ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated.  This fixes the new
RISC-V idle-states bindings to comply with the schema.

Fixes: 1bd524f7 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent a3dfc532

Documentation/devicetree/bindings/cpu/idle-states.yaml

+8 −8
Original line number Diff line number Diff line
@@ -719,8 +719,8 @@ examples: 
            reg = <0x0>;

            riscv,isa = "rv64imafdc";

            mmu-type = "riscv,sv48";

            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0

                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;

            cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,

                            <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;



            cpu_intc0: interrupt-controller {

                #interrupt-cells = <1>;
@@ -735,8 +735,8 @@ examples: 
            reg = <0x1>;

            riscv,isa = "rv64imafdc";

            mmu-type = "riscv,sv48";

            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0

                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;

            cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,

                            <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;



            cpu_intc1: interrupt-controller {

                #interrupt-cells = <1>;
@@ -751,8 +751,8 @@ examples: 
            reg = <0x10>;

            riscv,isa = "rv64imafdc";

            mmu-type = "riscv,sv48";

            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0

                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;

            cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,

                            <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;



            cpu_intc10: interrupt-controller {

                #interrupt-cells = <1>;
@@ -767,8 +767,8 @@ examples: 
            reg = <0x11>;

            riscv,isa = "rv64imafdc";

            mmu-type = "riscv,sv48";

            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0

                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;

            cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,

                            <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;



            cpu_intc11: interrupt-controller {

                #interrupt-cells = <1>;

Documentation/devicetree/bindings/riscv/cpus.yaml

+2 −0
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ properties: 


  cpu-idle-states:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    items:

      maxItems: 1

    description: |

      List of phandles to idle state nodes supported

      by this hart (see ./idle-states.yaml).