Commit 248b122b authored by Felipe Balbi's avatar Felipe Balbi
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usb: dwc3: core: fix cached revision on our structure 



All our revision macros are defined with the entire
32-bits which we read from GSNPSID register, so we
must cache all 32-bits properly rather than masking
the top 16-bits.

This will fix all revision checks we have on current
driver.

Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent ccc080c7

drivers/usb/dwc3/core.c

+1 −1
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc) 
		ret = -ENODEV;

		goto err0;

	}

	dwc->revision = reg & DWC3_GSNPSREV_MASK;

	dwc->revision = reg;



	dwc3_core_soft_reset(dwc);