Commit 247bdac9 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by Lucas De Marchi
Browse files

drm/i915/adl_p: Add ddb allocation support 



On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.

Bspec: 49255
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: default avatarClinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-8-lucas.demarchi@intel.com
parent 14076e46

drivers/gpu/drm/i915/i915_reg.h

+18 −4
Original line number Diff line number Diff line
@@ -7293,7 +7293,7 @@ enum { 


#define _PLANE_BUF_CFG_1_B			0x7127c

#define _PLANE_BUF_CFG_2_B			0x7137c

#define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */

#define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */

#define  DDB_ENTRY_END_SHIFT			16

#define _PLANE_BUF_CFG_1(pipe)	\

	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
@@ -8128,9 +8128,23 @@ enum { 
#define  DISP_DATA_PARTITION_5_6	(1 << 6)

#define  DISP_IPC_ENABLE		(1 << 3)



#define _DBUF_CTL_S1				0x45008

#define _DBUF_CTL_S2				0x44FE8

#define DBUF_CTL_S(slice)			_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))

/*

 * The below are numbered starting from "S1" on gen11/gen12, but starting

 * with gen13 display, the bspec switches to a 0-based numbering scheme

 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).

 * We'll just use the 0-based numbering here for all platforms since it's the

 * way things will be named by the hardware team going forward, plus it's more

 * consistent with how most of the rest of our registers are named.

 */

#define _DBUF_CTL_S0				0x45008

#define _DBUF_CTL_S1				0x44FE8

#define _DBUF_CTL_S2				0x44300

#define _DBUF_CTL_S3				0x44304

#define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \

							    _DBUF_CTL_S0, \

							    _DBUF_CTL_S1, \

							    _DBUF_CTL_S2, \

							    _DBUF_CTL_S3))

#define  DBUF_POWER_REQUEST			REG_BIT(31)

#define  DBUF_POWER_STATE			REG_BIT(30)

#define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)

drivers/gpu/drm/i915/intel_pm.c

+120 −1
Original line number Diff line number Diff line
@@ -4558,6 +4558,118 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = 
	{}

};



static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {

	{

		.active_pipes = BIT(PIPE_A),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_B),

		.dbuf_mask = {

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_C),

		.dbuf_mask = {

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),

		.dbuf_mask = {

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

		},

	},

	{

		.active_pipes = BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{

		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

		.dbuf_mask = {

			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),

			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),

			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),

		},

	},

	{}



};



static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,

			      const struct dbuf_slice_conf_entry *dbuf_slices)

{
@@ -4597,12 +4709,19 @@ static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) 
	return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);

}



static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)

{

	return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);

}



static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	if (DISPLAY_VER(dev_priv) == 12)

	if (IS_ALDERLAKE_P(dev_priv))

		return adlp_compute_dbuf_slices(pipe, active_pipes);

	else if (DISPLAY_VER(dev_priv) == 12)

		return tgl_compute_dbuf_slices(pipe, active_pipes);

	else if (DISPLAY_VER(dev_priv) == 11)

		return icl_compute_dbuf_slices(pipe, active_pipes);