Commit 24505bf0 authored by Weili Qian's avatar Weili Qian Committed by openeuler-sync-bot
Browse files

crypto: hisilicon/hpre - enable sva error interrupt event 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I7C6LD


CVE: NA

----------------------------------------------------------------------

Enable sva error interrupt event. When an error occurs on
the sva module, the device reports an abnormal interrupt to
the driver.

Fixes: 0fc481e4 ("crypto: hisilicon/hpre - add two RAS correctable errors processing")
Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
(cherry picked from commit cb8faaf0)
parent 879229e8

drivers/crypto/hisilicon/hpre/hpre_main.c

+4 −1
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { 
	{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},

	{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},

	{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xFFFFFE},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE},

	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE},

	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE},

	{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
@@ -278,6 +278,9 @@ static const struct hpre_hw_error hpre_hw_errors[] = { 
	}, {

		.int_msk = BIT(23),

		.msg = "sva_fsm_timeout_int_set"

	}, {

		.int_msk = BIT(24),

		.msg = "sva_int_set"

	}, {

		/* sentinel */

	}