Commit 2444733e authored by Sean Christopherson's avatar Sean Christopherson Committed by Yu Zhang
Browse files

KVM: x86/mmu: Add helper to generate mask of reserved HPA bits 

mainline inclusion
from mainline-v5.12-rc1
commit 6f8e65a6
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I7S3VQ
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6f8e65a60168567cc59f9b99980ea9112d4152f5



----------------------------------------------------------------------

Add a helper to generate the mask of reserved PA bits in the host.

No functional change intended.

Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20210204000117.3303214-10-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarYu Zhang <yu.c.zhang@linux.intel.com>
parent def4cf0d

arch/x86/kvm/mmu/mmu.c

+9 −5
Original line number Diff line number Diff line
@@ -4166,6 +4166,11 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, 
				    vcpu->arch.reserved_gpa_bits, execonly);

}



static inline u64 reserved_hpa_bits(void)

{

	return rsvd_bits(shadow_phys_bits, 63);

}



/*

 * the page table on host is the shadow page table for the page

 * table in guest or amd nested guest, its mmu features completely
@@ -4193,7 +4198,7 @@ reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) 
	 */

	shadow_zero_check = &context->shadow_zero_check;

	__reset_rsvds_bits_mask(vcpu, shadow_zero_check,

				rsvd_bits(shadow_phys_bits, 63),

				reserved_hpa_bits(),

				context->shadow_root_level, uses_nx,

				guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),

				is_pse(vcpu), true);
@@ -4230,14 +4235,13 @@ reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, 


	if (boot_cpu_is_amd())

		__reset_rsvds_bits_mask(vcpu, shadow_zero_check,

					rsvd_bits(shadow_phys_bits, 63),

					reserved_hpa_bits(),

					context->shadow_root_level, false,

					boot_cpu_has(X86_FEATURE_GBPAGES),

					true, true);

	else

		__reset_rsvds_bits_mask_ept(shadow_zero_check,

					    rsvd_bits(shadow_phys_bits, 63),

					    false);

					    reserved_hpa_bits(), false);



	if (!shadow_me_mask)

		return;
@@ -4257,7 +4261,7 @@ reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, 
				struct kvm_mmu *context, bool execonly)

{

	__reset_rsvds_bits_mask_ept(&context->shadow_zero_check,

				    rsvd_bits(shadow_phys_bits, 63), execonly);

				    reserved_hpa_bits(), execonly);

}



#define BYTE_MASK(access) \