Commit 2436387f authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata:
  arm64: errata: Remove AES hwcap for COMPAT tasks
  arm64: errata: Add Cortex-A510 to the repeat tlbi list
parents 322d19b6 44b3834b

Documentation/arm64/silicon-errata.rst

+6 −0
Original line number Diff line number Diff line
@@ -82,10 +82,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1319537        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1742098        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #853709         | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1319367        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1655431        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |
@@ -102,6 +106,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

arch/arm64/Kconfig

+33 −0
Original line number Diff line number Diff line
@@ -503,6 +503,22 @@ config ARM64_ERRATUM_834220 


	  If unsure, say Y.



config ARM64_ERRATUM_1742098

	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"

	depends on COMPAT

	default y

	help

	  This option removes the AES hwcap for aarch32 user-space to

	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.



	  Affected parts may corrupt the AES state if an interrupt is

	  taken between a pair of AES instructions. These instructions

	  are only present if the cryptography extensions are present.

	  All software should have a fallback implementation for CPUs

	  that don't implement the cryptography extensions.



	  If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on COMPAT
@@ -821,6 +837,23 @@ config ARM64_ERRATUM_2224489 


	  If unsure, say Y.



config ARM64_ERRATUM_2441009

	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"

	default y

	select ARM64_WORKAROUND_REPEAT_TLBI

	help

	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.



	  Under very rare circumstances, affected Cortex-A510 CPUs

	  may not handle a race between a break-before-make sequence on one

	  CPU, and another CPU accessing the same page. This could allow a

	  store to a page that has been unmapped.



	  Work around this by adding the affected CPUs to the list that needs

	  TLB sequences to be done twice.



	  If unsure, say Y.



config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on CORESIGHT_TRBE

arch/arm64/kernel/cpu_errata.c

+23 −1
Original line number Diff line number Diff line
@@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 
		/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */

		ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2441009

	{

		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),

	},

#endif

	{},

};
@@ -395,6 +401,14 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { 
};

#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */



#ifdef CONFIG_ARM64_ERRATUM_1742098

static struct midr_range broken_aarch32_aes[] = {

	MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

	{},

};

#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -480,7 +494,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI

	{

		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",

		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",

		.capability = ARM64_WORKAROUND_REPEAT_TLBI,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = cpucap_multi_entry_cap_matches,
@@ -657,6 +671,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		/* Cortex-A510 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1742098

	{

		.desc = "ARM erratum 1742098",

		.capability = ARM64_WORKAROUND_1742098,

		CAP_MIDR_RANGE_LIST(broken_aarch32_aes),

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

	},

#endif

	{

	}

arch/arm64/kernel/cpufeature.c

+13 −1
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 
#include <asm/cpufeature.h>

#include <asm/cpu_ops.h>

#include <asm/fpsimd.h>

#include <asm/hwcap.h>

#include <asm/insn.h>

#include <asm/kvm_host.h>

#include <asm/mmu_context.h>
@@ -1971,6 +1972,14 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 
}

#endif /* CONFIG_ARM64_MTE */



static void elf_hwcap_fixup(void)

{

#ifdef CONFIG_ARM64_ERRATUM_1742098

	if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))

		compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;

#endif /* ARM64_ERRATUM_1742098 */

}



#ifdef CONFIG_KVM

static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)

{
@@ -3143,8 +3152,10 @@ void __init setup_cpu_features(void) 
	setup_system_capabilities();

	setup_elf_hwcaps(arm64_elf_hwcaps);



	if (system_supports_32bit_el0())

	if (system_supports_32bit_el0()) {

		setup_elf_hwcaps(compat_elf_hwcaps);

		elf_hwcap_fixup();

	}



	if (system_uses_ttbr0_pan())

		pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
@@ -3197,6 +3208,7 @@ static int enable_mismatched_32bit_el0(unsigned int cpu) 
							 cpu_active_mask);

	get_cpu_device(lucky_winner)->offline_disabled = true;

	setup_elf_hwcaps(compat_elf_hwcaps);

	elf_hwcap_fixup();

	pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",

		cpu, lucky_winner);

	return 0;

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ WORKAROUND_1418040 
WORKAROUND_1463225

WORKAROUND_1508412

WORKAROUND_1542419

WORKAROUND_1742098

WORKAROUND_1902691

WORKAROUND_2038923

WORKAROUND_2064142