Commit 2435d790 authored by Poovendhan Selvaraj's avatar Poovendhan Selvaraj Committed by Bjorn Andersson
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arm64: dts: qcom: ipq9574: add support for RDP454 variant 



Add the initial device tree support for the Reference Design Platform (RDP)
454 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR and SMPA1 regulator node.

Signed-off-by: default avatarPoovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230531032648.23816-3-quic_poovendh@quicinc.com
parent add687cb

arch/arm64/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp433.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp449.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp453.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp454.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-acer-a1-724.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb

arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts

0 → 100644
+80 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * IPQ9574 RDP454 board device tree source

 *

 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.

 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.

 */



/dts-v1/;



#include "ipq9574.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";

	compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";



	aliases {

		serial0 = &blsp1_uart2;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&blsp1_spi0 {

	pinctrl-0 = <&spi_0_pins>;

	pinctrl-names = "default";

	status = "okay";



	flash@0 {

		compatible = "micron,n25q128a11", "jedec,spi-nor";

		reg = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		spi-max-frequency = <50000000>;

	};

};



&blsp1_uart2 {

	pinctrl-0 = <&uart2_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&rpm_requests {

	regulators {

		compatible = "qcom,rpm-mp5496-regulators";



		ipq9574_s1: s1 {

		/*

		 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.

		 * During regulator registration, kernel not knowing the initial voltage,

		 * considers it as zero and brings up the regulators with minimum supported voltage.

		 * Update the regulator-min-microvolt with SVS voltage of 725mV so that

		 * the regulators are brought up with 725mV which is sufficient for all the

		 * corner parts to operate at 800MHz

		 */

			regulator-min-microvolt = <725000>;

			regulator-max-microvolt = <1075000>;

		};

	};

};



&sleep_clk {

	clock-frequency = <32000>;

};



&tlmm {

	spi_0_pins: spi-0-state {

		pins = "gpio11", "gpio12", "gpio13", "gpio14";

		function = "blsp0_spi";

		drive-strength = <8>;

		bias-disable;

	};

};



&xo_board_clk {

	clock-frequency = <24000000>;

};