Commit 242da439 authored by Subbaraya Sundeep's avatar Subbaraya Sundeep Committed by David S. Miller
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octeontx2-af: cn10k: Add support for programmable channels 



NIX uses unique channel numbers to identify the packet sources/sinks
like CGX,LBK and SDP. The channel numbers assigned to each block are
hardwired in CN9xxx silicon.
The fixed channel numbers in CN9xxx are:

0x0 | a << 8 | b            - LBK(0..3)_CH(0..63)
0x0 | a << 8                - Reserved
0x700 | a                   - SDP_CH(0..255)
0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15)

All the channels in the above fixed enumerator(with maximum
number of blocks) are not required since some chips
have less number of blocks.
For CN10K silicon the channel numbers need to be programmed by
software in each block with the base channel number and range of
channels. This patch calculates and assigns the channel numbers
to efficiently distribute the channel number range(0-4095) among
all the blocks. The assignment is made based on the actual number of
blocks present and also contiguously leaving no holes.
The channel numbers remaining after the math are used as new CPT
replay channels present in CN10K. Also since channel numbers are
not fixed the transmit channel link number needed by AF consumers
is calculated by AF and sent along with nix_lf_alloc mailbox response.

Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: default avatarGeetha sowjanya <gakula@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 91c6945e

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -10720,6 +10720,7 @@ M: Linu Cherian <lcherian@marvell.com> 
M:	Geetha sowjanya <gakula@marvell.com>

M:	Jerin Jacob <jerinj@marvell.com>

M:	hariprasad <hkelam@marvell.com>

M:	Subbaraya Sundeep <sbhatta@marvell.com>

L:	netdev@vger.kernel.org

S:	Supported

F:	Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -10,4 +10,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o 
octeontx2_mbox-y := mbox.o rvu_trace.o

octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o
 
		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+14 −0
Original line number Diff line number Diff line
@@ -123,6 +123,20 @@ void *cgx_get_pdata(int cgx_id) 
	return NULL;

}



void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)

{

	struct cgx *cgx_dev = cgx_get_pdata(cgx_id);



	cgx_write(cgx_dev, lmac_id, offset, val);

}



u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)

{

	struct cgx *cgx_dev = cgx_get_pdata(cgx_id);



	return cgx_read(cgx_dev, lmac_id, offset);

}



int cgx_get_cgxid(void *cgxd)

{

	struct cgx *cgx = cgxd;

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+2 −0
Original line number Diff line number Diff line
@@ -162,4 +162,6 @@ struct mac_ops *get_mac_ops(void *cgxd); 
int cgx_get_nr_lmacs(void *cgxd);

u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);

unsigned long cgx_get_lmac_bmap(void *cgxd);

void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);

u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);

#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/common.h

+3 −0
Original line number Diff line number Diff line
@@ -191,6 +191,9 @@ enum nix_scheduler { 
#define NIX_LINK_LBK(a)			(12 + (a))

#define NIX_CHAN_CGX_LMAC_CHX(a, b, c)	(0x800 + 0x100 * (a) + 0x10 * (b) + (c))

#define NIX_CHAN_LBK_CHX(a, b)		(0 + 0x100 * (a) + (b))

#define NIX_CHAN_SDP_CH_START		(0x700ull)



#define SDP_CHANNELS			256



/* NIX LSO format indices.

 * As of now TSO is the only one using, so statically assigning indices.