Unverified Commit 241a9e23 authored by Marek Vasut's avatar Marek Vasut Committed by Robert Foss
Browse files

drm/bridge: ti-sn65dsi83: Fix sparse warnings 



Fix the following sparse warnings generated by "make C=1":

drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: warning: incorrect type in assignment (different base types)
drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13:    expected unsigned short [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13:    got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: warning: incorrect type in assignment (different base types)
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13:    expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13:    got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: warning: incorrect type in assignment (different base types)
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13:    expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13:    got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: warning: incorrect type in assignment (different base types)
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13:    expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13:    got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: warning: incorrect type in assignment (different base types)
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13:    expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13:    got restricted __le16 [usertype]

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Loic Poulain <loic.poulain@linaro.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Philippe Schenker <philippe.schenker@toradex.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Valentin Raevsky <valentin@compulab.co.il>
To: dri-devel@lists.freedesktop.org
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarRobert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210608142211.82333-1-marex@denx.de
parent 5b7a2c92

drivers/gpu/drm/bridge/ti-sn65dsi83.c

+11 −10
Original line number Diff line number Diff line
@@ -368,6 +368,7 @@ static void sn65dsi83_enable(struct drm_bridge *bridge) 
{

	struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);

	unsigned int pval;

	__le16 le16val;

	u16 val;

	int ret;
@@ -426,21 +427,21 @@ static void sn65dsi83_enable(struct drm_bridge *bridge) 
		     REG_LVDS_LANE_CHB_LVDS_TERM);

	regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);



	val = cpu_to_le16(ctx->mode.hdisplay);

	le16val = cpu_to_le16(ctx->mode.hdisplay);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,

			  &val, 2);

	val = cpu_to_le16(ctx->mode.vdisplay);

			  &le16val, 2);

	le16val = cpu_to_le16(ctx->mode.vdisplay);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,

			  &val, 2);

			  &le16val, 2);

	/* 32 + 1 pixel clock to ensure proper operation */

	val = cpu_to_le16(32 + 1);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &val, 2);

	val = cpu_to_le16(ctx->mode.hsync_end - ctx->mode.hsync_start);

	le16val = cpu_to_le16(32 + 1);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);

	le16val = cpu_to_le16(ctx->mode.hsync_end - ctx->mode.hsync_start);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,

			  &val, 2);

	val = cpu_to_le16(ctx->mode.vsync_end - ctx->mode.vsync_start);

			  &le16val, 2);

	le16val = cpu_to_le16(ctx->mode.vsync_end - ctx->mode.vsync_start);

	regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,

			  &val, 2);

			  &le16val, 2);

	regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,

		     ctx->mode.htotal - ctx->mode.hsync_end);

	regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,