Commit 23e4aa51 authored by shaoyunl's avatar shaoyunl Committed by Alex Deucher
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drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime 



On SRIOV, driver should only access register through RLC in runtime

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarshaoyunl <shaoyun.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 30d95a37

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+2 −2
Original line number Diff line number Diff line
@@ -28,12 +28,12 @@ 
#define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)



#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \

	((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \

	 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \

	 WREG32(reg, value))



#define __RREG32_SOC15_RLC__(reg, flag, hwip) \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \

	((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \

	 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \

	 RREG32(reg))