Commit 23b04c84 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: div6: Simplify src mask handling 



Simplify the handling of the register bits to select the parent clock,
by storing a bitmask instead of separate shift and width values.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5f05a5110d222ce5a113e683fe2aa726f4100b73.1617281699.git.geert+renesas@glider.be
parent 6c7bc7db

drivers/clk/renesas/clk-div6.c

+11 −20
Original line number Original line Diff line number Diff line
@@ -28,8 +28,7 @@ 
 * @hw: handle between common and hardware-specific interfaces

 * @hw: handle between common and hardware-specific interfaces

 * @reg: IO-remapped register

 * @reg: IO-remapped register

 * @div: divisor value (1-64)

 * @div: divisor value (1-64)

 * @src_shift: Shift to access the register bits to select the parent clock

 * @src_mask: Bitmask covering the register bits to select the parent clock

 * @src_width: Number of register bits to select the parent clock (may be 0)

 * @nb: Notifier block to save/restore clock state for system resume

 * @nb: Notifier block to save/restore clock state for system resume

 * @parents: Array to map from valid parent clocks indices to hardware indices

 * @parents: Array to map from valid parent clocks indices to hardware indices

 */

 */
@@ -37,8 +36,7 @@ struct div6_clock { 
	struct clk_hw hw;

	struct clk_hw hw;

	void __iomem *reg;

	void __iomem *reg;

	unsigned int div;

	unsigned int div;

	u32 src_shift;

	u32 src_mask;

	u32 src_width;

	struct notifier_block nb;

	struct notifier_block nb;

	u8 parents[];

	u8 parents[];

};

};
@@ -133,11 +131,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) 
	unsigned int i;

	unsigned int i;

	u8 hw_index;

	u8 hw_index;





	if (clock->src_width == 0)

	if (clock->src_mask == 0)

		return 0;

		return 0;





	hw_index = (readl(clock->reg) >> clock->src_shift) &

	hw_index = (readl(clock->reg) & clock->src_mask) >>

		   (BIT(clock->src_width) - 1);

		   __ffs(clock->src_mask);

	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {

	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {

		if (clock->parents[i] == hw_index)

		if (clock->parents[i] == hw_index)

			return i;

			return i;
@@ -151,18 +149,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) 
static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)

static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)

{

{

	struct div6_clock *clock = to_div6_clock(hw);

	struct div6_clock *clock = to_div6_clock(hw);

	u8 hw_index;

	u32 src;

	u32 mask;





	if (index >= clk_hw_get_num_parents(hw))

	if (index >= clk_hw_get_num_parents(hw))

		return -EINVAL;

		return -EINVAL;





	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);

	src = clock->parents[index] << __ffs(clock->src_mask);

	hw_index = clock->parents[index];

	writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);



	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),

	       clock->reg);



	return 0;

	return 0;

}

}
@@ -236,17 +229,15 @@ struct clk * __init cpg_div6_register(const char *name, 
	switch (num_parents) {

	switch (num_parents) {

	case 1:

	case 1:

		/* fixed parent clock */

		/* fixed parent clock */

		clock->src_shift = clock->src_width = 0;

		clock->src_mask = 0;

		break;

		break;

	case 4:

	case 4:

		/* clock with EXSRC bits 6-7 */

		/* clock with EXSRC bits 6-7 */

		clock->src_shift = 6;

		clock->src_mask = GENMASK(7, 6);

		clock->src_width = 2;

		break;

		break;

	case 8:

	case 8:

		/* VCLK with EXSRC bits 12-14 */

		/* VCLK with EXSRC bits 12-14 */

		clock->src_shift = 12;

		clock->src_mask = GENMASK(14, 12);

		clock->src_width = 3;

		break;

		break;

	default:

	default:

		pr_err("%s: invalid number of parents for DIV6 clock %s\n",

		pr_err("%s: invalid number of parents for DIV6 clock %s\n",