Commit 237e7be0 authored by Mika Kahola's avatar Mika Kahola Committed by Radhakrishna Sripada
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drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA 



Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled.

v2: Fix typo in commit message (Animesh)

Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-7-mika.kahola@intel.com
parent ac50317e

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+5 −2
Original line number Diff line number Diff line
@@ -2349,7 +2349,10 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 
		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);



	/* TODO: HDMI FRL */

	/* TODO: DP2.0 10G and 20G rates enable MPLLA*/

	/* DP2.0 10G and 20G rates enable MPLLA*/

	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)

		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;

	else

		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;



	intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),