Loading arch/x86/events/intel/core.c +10 −6 Original line number Diff line number Diff line Loading @@ -2521,6 +2521,8 @@ static int adl_set_topdown_event_period(struct perf_event *event) return icl_set_topdown_event_period(event); } DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) { u32 val; Loading Loading @@ -2811,9 +2813,8 @@ int intel_pmu_save_and_restart(struct perf_event *event) static int intel_pmu_set_period(struct perf_event *event) { if (unlikely(is_topdown_count(event)) && x86_pmu.set_topdown_event_period) return x86_pmu.set_topdown_event_period(event); if (unlikely(is_topdown_count(event))) return static_call(intel_pmu_set_topdown_event_period)(event); return x86_perf_event_set_period(event); } Loading Loading @@ -6292,7 +6293,8 @@ __init int intel_pmu_init(void) intel_pmu_pebs_data_source_skl(pmem); x86_pmu.num_topdown_events = 4; x86_pmu.update_topdown_event = icl_update_topdown_event; x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &icl_set_topdown_event_period); pr_cont("Icelake events, "); name = "icelake"; break; Loading Loading @@ -6330,7 +6332,8 @@ __init int intel_pmu_init(void) intel_pmu_pebs_data_source_skl(pmem); x86_pmu.num_topdown_events = 8; x86_pmu.update_topdown_event = icl_update_topdown_event; x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &icl_set_topdown_event_period); pr_cont("Sapphire Rapids events, "); name = "sapphire_rapids"; break; Loading Loading @@ -6367,7 +6370,8 @@ __init int intel_pmu_init(void) x86_pmu.pebs_latency_data = adl_latency_data_small; x86_pmu.num_topdown_events = 8; x86_pmu.update_topdown_event = adl_update_topdown_event; x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &adl_set_topdown_event_period); x86_pmu.filter_match = intel_pmu_filter_match; x86_pmu.get_event_constraints = adl_get_event_constraints; Loading arch/x86/events/perf_event.h +0 −1 Original line number Diff line number Diff line Loading @@ -890,7 +890,6 @@ struct x86_pmu { */ int num_topdown_events; u64 (*update_topdown_event)(struct perf_event *event); int (*set_topdown_event_period)(struct perf_event *event); /* * perf task context (i.e. struct perf_event_context::task_ctx_data) Loading Loading
arch/x86/events/intel/core.c +10 −6 Original line number Diff line number Diff line Loading @@ -2521,6 +2521,8 @@ static int adl_set_topdown_event_period(struct perf_event *event) return icl_set_topdown_event_period(event); } DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) { u32 val; Loading Loading @@ -2811,9 +2813,8 @@ int intel_pmu_save_and_restart(struct perf_event *event) static int intel_pmu_set_period(struct perf_event *event) { if (unlikely(is_topdown_count(event)) && x86_pmu.set_topdown_event_period) return x86_pmu.set_topdown_event_period(event); if (unlikely(is_topdown_count(event))) return static_call(intel_pmu_set_topdown_event_period)(event); return x86_perf_event_set_period(event); } Loading Loading @@ -6292,7 +6293,8 @@ __init int intel_pmu_init(void) intel_pmu_pebs_data_source_skl(pmem); x86_pmu.num_topdown_events = 4; x86_pmu.update_topdown_event = icl_update_topdown_event; x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &icl_set_topdown_event_period); pr_cont("Icelake events, "); name = "icelake"; break; Loading Loading @@ -6330,7 +6332,8 @@ __init int intel_pmu_init(void) intel_pmu_pebs_data_source_skl(pmem); x86_pmu.num_topdown_events = 8; x86_pmu.update_topdown_event = icl_update_topdown_event; x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &icl_set_topdown_event_period); pr_cont("Sapphire Rapids events, "); name = "sapphire_rapids"; break; Loading Loading @@ -6367,7 +6370,8 @@ __init int intel_pmu_init(void) x86_pmu.pebs_latency_data = adl_latency_data_small; x86_pmu.num_topdown_events = 8; x86_pmu.update_topdown_event = adl_update_topdown_event; x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; static_call_update(intel_pmu_set_topdown_event_period, &adl_set_topdown_event_period); x86_pmu.filter_match = intel_pmu_filter_match; x86_pmu.get_event_constraints = adl_get_event_constraints; Loading
arch/x86/events/perf_event.h +0 −1 Original line number Diff line number Diff line Loading @@ -890,7 +890,6 @@ struct x86_pmu { */ int num_topdown_events; u64 (*update_topdown_event)(struct perf_event *event); int (*set_topdown_event_period)(struct perf_event *event); /* * perf task context (i.e. struct perf_event_context::task_ctx_data) Loading