Unverified Commit 2367ee1a authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'samsung-dt64-5.19-2' of... 

Merge tag 'samsung-dt64-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v5.19, part two

1. Cleanups: unused and undocumented dma-channels and dma-requests.
2. Add clock controllers to ExynosAutov9.

* tag 'samsung-dt64-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: switch UFS clock node in ExynosAutov9
  arm64: dts: exynos: switch USI clocks in ExynosAutov9
  arm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9
  dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings
  dt-bindings: clock: add clock binding definitions for Exynos Auto v9
  arm64: dts: fsd: drop useless 'dma-channels/requests' properties
  arm64: dts: exynos: drop useless 'dma-channels/requests' properties
  arm64: dts: exynos: move XTCXO clock frequency to board in Exynos Auto v9

Link: https://lore.kernel.org/r/20220506081438.149192-5-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c86071e8 98829483

Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos Auto v9 SoC clock controller



maintainers:

  - Chanho Park <chanho61.park@samsung.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Sylwester Nawrocki <s.nawrocki@samsung.com>

  - Tomasz Figa <tomasz.figa@gmail.com>



description: |

  Exynos Auto v9 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. Root clocks in that clock tree are

  two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).

  The external OSCCLK must be defined as fixed-rate clock in dts.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/samsung,exynosautov9.h' header.



properties:

  compatible:

    enum:

      - samsung,exynosautov9-cmu-top

      - samsung,exynosautov9-cmu-busmc

      - samsung,exynosautov9-cmu-core

      - samsung,exynosautov9-cmu-fsys2

      - samsung,exynosautov9-cmu-peric0

      - samsung,exynosautov9-cmu-peric1

      - samsung,exynosautov9-cmu-peris



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)



        clock-names:

          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-busmc



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_BUSMC bus clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_busmc_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-core



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_CORE bus clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_core_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-fsys2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS2 bus clock (from CMU_TOP)

            - description: UFS clock (from CMU_TOP)

            - description: Ethernet clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_fsys2_bus

            - const: dout_fsys2_clkcmu_ufs_embd

            - const: dout_fsys2_clkcmu_ethernet



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-peric0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIC0 bus clock (from CMU_TOP)

            - description: PERIC0 IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_peric0_bus

            - const: dout_clkcmu_peric0_ip



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-peric1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIC1 bus clock (from CMU_TOP)

            - description: PERIC1 IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_peric1_bus

            - const: dout_clkcmu_peric1_ip



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-peris



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIS bus clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_peris_bus



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names

  - reg



additionalProperties: false



examples:

  # Clock controller node for CMU_FSYS2

  - |

    #include <dt-bindings/clock/samsung,exynosautov9.h>



    cmu_fsys2: clock-controller@17c00000 {

        compatible = "samsung,exynosautov9-cmu-fsys2";

        reg = <0x17c00000 0x8000>;

        #clock-cells = <1>;



        clocks = <&xtcxo>,

                 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,

                 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,

                 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;

        clock-names = "oscclk",

                      "dout_clkcmu_fsys2_bus",

                      "dout_fsys2_clkcmu_ufs_embd",

                      "dout_fsys2_clkcmu_ethernet";

    };



...

arch/arm64/boot/dts/exynos/exynos5433.dtsi

+0 −6
Original line number Diff line number Diff line
@@ -1866,8 +1866,6 @@ 
			clocks = <&cmu_fsys CLK_PDMA0>;

			clock-names = "apb_pclk";

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <32>;

		};



		pdma1: dma-controller@15600000 {
@@ -1877,8 +1875,6 @@ 
			clocks = <&cmu_fsys CLK_PDMA1>;

			clock-names = "apb_pclk";

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <32>;

		};



		audio-subsystem@11400000 {
@@ -1898,8 +1894,6 @@ 
				clocks = <&cmu_aud CLK_ACLK_DMAC>;

				clock-names = "apb_pclk";

				#dma-cells = <1>;

				#dma-channels = <8>;

				#dma-requests = <32>;

				power-domains = <&pd_aud>;

			};

arch/arm64/boot/dts/exynos/exynos7.dtsi

+0 −4
Original line number Diff line number Diff line
@@ -149,8 +149,6 @@ 
			clocks = <&clock_fsys0 ACLK_PDMA0>;

			clock-names = "apb_pclk";

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <32>;

		};



		pdma1: dma-controller@10eb0000 {
@@ -160,8 +158,6 @@ 
			clocks = <&clock_fsys0 ACLK_PDMA1>;

			clock-names = "apb_pclk";

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <32>;

		};



		clock_topc: clock-controller@10570000 {

arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts

+4 −0
Original line number Diff line number Diff line
@@ -58,3 +58,7 @@ 
&usi_0 {

	status = "okay";

};



&xtcxo {

	clock-frequency = <26000000>;

};

arch/arm64/boot/dts/exynos/exynosautov9.dtsi

+90 −26
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 *

 */



#include <dt-bindings/clock/samsung,exynosautov9.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -153,30 +154,8 @@ 
		xtcxo: clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <26000000>;

			clock-output-names = "oscclk";

		};



		/*

		 * Keep the stub clock for serial driver, until proper clock

		 * driver is implemented.

		 */

		uart_clock: uart-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <133250000>;

			clock-output-names = "uart";

		};



		/*

		 * Keep the stub clock for ufs driver, until proper clock

		 * driver is implemented.

		 */

		ufs_core_clock: ufs-core-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <166562500>;

		};

	};



	soc: soc@0 {
@@ -190,6 +169,89 @@ 
			reg = <0x10000000 0x24>;

		};



		cmu_peris: clock-controller@10020000 {

			compatible = "samsung,exynosautov9-cmu-peris";

			reg = <0x10020000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;

			clock-names = "oscclk",

				      "dout_clkcmu_peris_bus";

		};



		cmu_peric0: clock-controller@10200000 {

			compatible = "samsung,exynosautov9-cmu-peric0";

			reg = <0x10200000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,

				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;

			clock-names = "oscclk",

				      "dout_clkcmu_peric0_bus",

				      "dout_clkcmu_peric0_ip";

		};



		cmu_peric1: clock-controller@10800000 {

			compatible = "samsung,exynosautov9-cmu-peric1";

			reg = <0x10800000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,

				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;

			clock-names = "oscclk",

				      "dout_clkcmu_peric1_bus",

				      "dout_clkcmu_peric1_ip";

		};



		cmu_fsys2: clock-controller@17c00000 {

			compatible = "samsung,exynosautov9-cmu-fsys2";

			reg = <0x17c00000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,

				 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,

				 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;

			clock-names = "oscclk",

				      "dout_clkcmu_fsys2_bus",

				      "dout_fsys2_clkcmu_ufs_embd",

				      "dout_fsys2_clkcmu_ethernet";

		};



		cmu_core: clock-controller@1b030000 {

			compatible = "samsung,exynosautov9-cmu-core";

			reg = <0x1b030000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_CORE_BUS>;

			clock-names = "oscclk",

				      "dout_clkcmu_core_bus";

		};



		cmu_busmc: clock-controller@1b200000 {

			compatible = "samsung,exynosautov9-cmu-busmc";

			reg = <0x1b200000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>,

				 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>;

			clock-names = "oscclk",

				      "dout_clkcmu_busmc_bus";

		};



		cmu_top: clock-controller@1b240000 {

			compatible = "samsung,exynosautov9-cmu-top";

			reg = <0x1b240000 0x8000>;

			#clock-cells = <1>;



			clocks = <&xtcxo>;

			clock-names = "oscclk";

		};



		gic: interrupt-controller@10101000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;
@@ -271,7 +333,8 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			clocks = <&uart_clock>, <&uart_clock>;

			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,

				 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;

			clock-names = "pclk", "ipclk";

			status = "disabled";
@@ -282,7 +345,8 @@ 
				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&uart0_bus_dual>;

				clocks = <&uart_clock>, <&uart_clock>;

				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,

					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;

				clock-names = "uart", "clk_uart_baud0";

				status = "disabled";

			};
@@ -308,8 +372,8 @@ 
				<0x17dc0000 0x2200>;  /* 3: UFS protector */

			reg-names = "hci", "vs_hci", "unipro", "ufsp";

			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ufs_core_clock>,

				<&ufs_core_clock>;

			clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,

				 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>;

			clock-names = "core_clk", "sclk_unipro_main";

			freq-table-hz = <0 0>, <0 0>;

			pinctrl-names = "default";