Commit 2353828f authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm 

Pull ARM cpufreq updates for 5.18-rc1 fron Viresh Kumar:

"- Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml
   binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers
   (Luca Weiss).

 - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner).

 - Fix CPPC driver's freq/performance conversions (Pierre Gondois).

 - Minor generic cleanups (Yury Norov)."

* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings
  dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example
  cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev
  cpufreq: qcom-hw: Add support for per-core-dcvs
  cpufreq: CPPC: Fix performance/frequency conversion
  cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist
  ARM: dts: imx7s: Define operating points table for cpufreq
  cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse
  cpufreq: replace cpumask_weight with cpumask_empty where appropriate
parents 02b82b02 b7f2b0d3

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt

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Qualcomm Technologies, Inc. CPUFREQ Bindings



CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)

SoCs to manage frequency in hardware. It is capable of controlling frequency

for multiple clusters.



Properties:

- compatible

	Usage:		required

	Value type:	<string>

	Definition:	must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".



- clocks

	Usage:		required

	Value type:	<phandle> From common clock binding.

	Definition:	clock handle for XO clock and GPLL0 clock.



- clock-names

	Usage:		required

	Value type:	<string> From common clock binding.

	Definition:	must be "xo", "alternate".



- reg

	Usage:		required

	Value type:	<prop-encoded-array>

	Definition:	Addresses and sizes for the memory of the HW bases in

			each frequency domain.

- reg-names

	Usage:		Optional

	Value type:	<string>

	Definition:	Frequency domain name i.e.

			"freq-domain0", "freq-domain1".



- #freq-domain-cells:

	Usage:		required.

	Definition:	Number of cells in a freqency domain specifier.



* Property qcom,freq-domain

Devices supporting freq-domain must set their "qcom,freq-domain" property with

phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.





Example:



Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch

DCVS state together.



/ {

	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				      compatible = "cache";

				};

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_100: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_200: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_300: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_400: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_500: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_600: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_700: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};

	};



 soc {

	cpufreq_hw: cpufreq@17d43000 {

		compatible = "qcom,cpufreq-hw";

		reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;

		reg-names = "freq-domain0", "freq-domain1";



		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";



		#freq-domain-cells = <1>;

	};

}

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. CPUFREQ



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |



  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)

  SoCs to manage frequency in hardware. It is capable of controlling frequency

  for multiple clusters.



properties:

  compatible:

    oneOf:

      - description: v1 of CPUFREQ HW

        items:

          - const: qcom,cpufreq-hw



      - description: v2 of CPUFREQ HW (EPSS)

        items:

          - enum:

              - qcom,sm8250-cpufreq-epss

          - const: qcom,cpufreq-epss



  reg:

    minItems: 2

    items:

      - description: Frequency domain 0 register region

      - description: Frequency domain 1 register region

      - description: Frequency domain 2 register region



  reg-names:

    minItems: 2

    items:

      - const: freq-domain0

      - const: freq-domain1

      - const: freq-domain2



  clocks:

    items:

      - description: XO Clock

      - description: GPLL0 Clock



  clock-names:

    items:

      - const: xo

      - const: alternate



  '#freq-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#freq-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/clock/qcom,rpmh.h>



    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster

    // switch DCVS state together.

    cpus {

      #address-cells = <2>;

      #size-cells = <0>;



      CPU0: cpu@0 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x0>;

        enable-method = "psci";

        next-level-cache = <&L2_0>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        L2_0: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

          L3_0: l3-cache {

            compatible = "cache";

          };

        };

      };



      CPU1: cpu@100 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x100>;

        enable-method = "psci";

        next-level-cache = <&L2_100>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        L2_100: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU2: cpu@200 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x200>;

        enable-method = "psci";

        next-level-cache = <&L2_200>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        L2_200: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU3: cpu@300 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x300>;

        enable-method = "psci";

        next-level-cache = <&L2_300>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        L2_300: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU4: cpu@400 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x400>;

        enable-method = "psci";

        next-level-cache = <&L2_400>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        L2_400: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU5: cpu@500 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x500>;

        enable-method = "psci";

        next-level-cache = <&L2_500>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        L2_500: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU6: cpu@600 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x600>;

        enable-method = "psci";

        next-level-cache = <&L2_600>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        L2_600: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };



      CPU7: cpu@700 {

        device_type = "cpu";

        compatible = "qcom,kryo385";

        reg = <0x0 0x700>;

        enable-method = "psci";

        next-level-cache = <&L2_700>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        L2_700: l2-cache {

          compatible = "cache";

          next-level-cache = <&L3_0>;

        };

      };

    };



    soc {

      #address-cells = <1>;

      #size-cells = <1>;



      cpufreq@17d43000 {

        compatible = "qcom,cpufreq-hw";

        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;

        reg-names = "freq-domain0", "freq-domain1";



        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

        clock-names = "xo", "alternate";



        #freq-domain-cells = <1>;

      };

    };

...

Documentation/devicetree/bindings/dvfs/performance-domain.yaml

+10 −4
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@@ -52,11 +52,17 @@ additionalProperties: true 


examples:

  - |

    performance: performance-controller@12340000 {

        compatible = "qcom,cpufreq-hw";

        reg = <0x12340000 0x1000>;

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        performance: performance-controller@11bc00 {

            compatible = "mediatek,cpufreq-hw";

            reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;



            #performance-domain-cells = <1>;

        };

    };



    // The node above defines a performance controller that is a performance

    // domain provider and expects one cell as its phandle argument.

arch/arm/boot/dts/imx7s.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -76,6 +76,22 @@ 
			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clks IMX7D_CLK_ARM>;

			cpu-idle-states = <&cpu_sleep_wait>;

			operating-points-v2 = <&cpu0_opp_table>;

			#cooling-cells = <2>;

			nvmem-cells = <&fuse_grade>;

			nvmem-cell-names = "speed_grade";

		};

	};



	cpu0_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-792000000 {

			opp-hz = /bits/ 64 <792000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <150000>;

			opp-supported-hw = <0xf>, <0xf>;

		};

	};

drivers/cpufreq/cppc_cpufreq.c

+21 −22
Original line number Diff line number Diff line
@@ -303,52 +303,48 @@ static u64 cppc_get_dmi_max_khz(void) 


/*

 * If CPPC lowest_freq and nominal_freq registers are exposed then we can

 * use them to convert perf to freq and vice versa

 *

 * If the perf/freq point lies between Nominal and Lowest, we can treat

 * (Low perf, Low freq) and (Nom Perf, Nom freq) as 2D co-ordinates of a line

 * and extrapolate the rest

 * For perf/freq > Nominal, we use the ratio perf:freq at Nominal for conversion

 * use them to convert perf to freq and vice versa. The conversion is

 * extrapolated as an affine function passing by the 2 points:

 *  - (Low perf, Low freq)

 *  - (Nominal perf, Nominal perf)

 */

static unsigned int cppc_cpufreq_perf_to_khz(struct cppc_cpudata *cpu_data,

					     unsigned int perf)

{

	struct cppc_perf_caps *caps = &cpu_data->perf_caps;

	s64 retval, offset = 0;

	static u64 max_khz;

	u64 mul, div;



	if (caps->lowest_freq && caps->nominal_freq) {

		if (perf >= caps->nominal_perf) {

			mul = caps->nominal_freq;

			div = caps->nominal_perf;

		} else {

		mul = caps->nominal_freq - caps->lowest_freq;

		div = caps->nominal_perf - caps->lowest_perf;

		}

		offset = caps->nominal_freq - div64_u64(caps->nominal_perf * mul, div);

	} else {

		if (!max_khz)

			max_khz = cppc_get_dmi_max_khz();

		mul = max_khz;

		div = caps->highest_perf;

	}

	return (u64)perf * mul / div;



	retval = offset + div64_u64(perf * mul, div);

	if (retval >= 0)

		return retval;

	return 0;

}



static unsigned int cppc_cpufreq_khz_to_perf(struct cppc_cpudata *cpu_data,

					     unsigned int freq)

{

	struct cppc_perf_caps *caps = &cpu_data->perf_caps;

	s64 retval, offset = 0;

	static u64 max_khz;

	u64  mul, div;



	if (caps->lowest_freq && caps->nominal_freq) {

		if (freq >= caps->nominal_freq) {

			mul = caps->nominal_perf;

			div = caps->nominal_freq;

		} else {

			mul = caps->lowest_perf;

			div = caps->lowest_freq;

		}

		mul = caps->nominal_perf - caps->lowest_perf;

		div = caps->nominal_freq - caps->lowest_freq;

		offset = caps->nominal_perf - div64_u64(caps->nominal_freq * mul, div);

	} else {

		if (!max_khz)

			max_khz = cppc_get_dmi_max_khz();
@@ -356,7 +352,10 @@ static unsigned int cppc_cpufreq_khz_to_perf(struct cppc_cpudata *cpu_data, 
		div = max_khz;

	}



	return (u64)freq * mul / div;

	retval = offset + div64_u64(freq * mul, div);

	if (retval >= 0)

		return retval;

	return 0;

}



static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,