Commit 234af44f authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'qcom-clk-for-5.18' of...

Merge tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

This introduces support for A7 PLL on SDX65, GPU clock controller for
SM6350, display clock controller for SM6125, SM6350 and QCS2290 and
multimedia clock controller for MSM8226. The RPMCC drivers get support
for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks.

A new gcc DeviceTree binding is introduced, to allow platform-specific
GCC bindings to inherit common properties. The SDM845 camera clock
controller binding is converted to YAML.

SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074
global clock controller, IPQ806x global clock controller, SC7180 camera
and video clock controllers, MSM8996 globacl clock controller are
converted to parent_data and/or parent_hws and cleanups related to this.

Test clocks are removed from the SC7180, SDM845 camera clock controller
drivers and SDM660 GPU clock controller driver.

IPQ806x gains clocks and resets for CryptoEngine and additional
frequencies for SDCC and NSS cores.

Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC
clocks.

SM8150 gains EMAC, PCIe and UFS GDSCs.

The RCG2 logic for calculating D value is updated to support pixel clock
frequencies on newer platforms.

* tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits)
  clk: qcom: Add display clock controller driver for SM6125
  dt-bindings: clock: add QCOM SM6125 display clock bindings
  clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig
  clk: qcom: gcc: Add emac GDSC support for SM8150
  clk: qcom: gcc: sm8150: Fix some identation issues
  clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150
  clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
  clk: qcom: clk-rcg2: Update the frac table for pixel clock
  clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
  clk: qcom: smd: Add missing MSM8998 RPM clocks
  clk: qcom: smd: Add missing RPM clocks for msm8992/4
  dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks
  clk: qcom: gcc-ipq806x: add CryptoEngine resets
  dt-bindings: reset: add ipq8064 ce5 resets
  clk: qcom: gcc-ipq806x: add CryptoEngine clocks
  dt-bindings: clock: add ipq8064 ce5 clk define
  clk: qcom: gcc-ipq806x: add additional freq for sdc table
  clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
  clk: qcom: gcc-ipq806x: add unusued flag for critical clock
  clk: qcom: gcc-ipq806x: add additional freq nss cores
  ...
parents e783362e 6e87c8f0
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@@ -10,7 +10,7 @@ maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
  The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
  frequency clock to the CPU.

properties:
+0 −18
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Qualcomm Camera Clock & Reset Controller Binding
------------------------------------------------

Required properties :
- compatible : shall contain "qcom,sdm845-camcc".
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.
- #power-domain-cells : from generic power domain binding, shall contain 1.

Example:
	camcc: clock-controller@ad00000 {
		compatible = "qcom,sdm845-camcc";
		reg = <0xad00000 0x10000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;
	};
+87 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock Controller Binding for SM6125

maintainers:
  - Martin Botka <martin.botka@somainline.org>

description: |
  Qualcomm display clock control module which supports the clocks and
  power domains on SM6125.

  See also:
    dt-bindings/clock/qcom,dispcc-sm6125.h

properties:
  compatible:
    enum:
      - qcom,sm6125-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY
      - description: AHB config clock from GCC

  clock-names:
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk
      - const: cfg_ahb_clk

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
    clock-controller@5f00000 {
      compatible = "qcom,sm6125-dispcc";
      reg = <0x5f00000 0x20000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>,
               <&gcc GCC_DISP_AHB_CLK>;
      clock-names = "bi_tcxo",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dsi1_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk",
                    "cfg_ahb_clk";
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };
...
+86 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller Binding for SM6350

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains on SM6350.

  See also dt-bindings/clock/qcom,dispcc-sm6350.h.

properties:
  compatible:
    const: qcom,sm6350-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sm6350-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK>,
               <&dsi_phy 0>,
               <&dsi_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
+7 −22
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@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller Binding for APQ8064

allOf:
  - $ref: qcom,gcc.yaml#

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>
@@ -17,22 +20,12 @@ description: |
  See also:
  - dt-bindings/clock/qcom,gcc-msm8960.h
  - dt-bindings/reset/qcom,gcc-msm8960.h
  - dt-bindings/clock/qcom,gcc-apq8084.h
  - dt-bindings/reset/qcom,gcc-apq8084.h

properties:
  compatible:
    const: qcom,gcc-apq8064

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1
    const: qcom,gcc-apq8084

  nvmem-cells:
    minItems: 1
@@ -53,21 +46,13 @@ properties:
  '#thermal-sensor-cells':
    const: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding.

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'
  - nvmem-cells
  - nvmem-cell-names
  - '#thermal-sensor-cells'

additionalProperties: false
unevaluatedProperties: false

examples:
  - |
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