Commit 232ccac1 authored by Samuel Holland's avatar Samuel Holland Committed by Daniel Lezcano
Browse files

clocksource/drivers/riscv: Events are stopped during CPU suspend 



Some implementations of the SBI time extension depend on hart-local
state (for example, CSRs) that are lost or hardware that is powered
down when a CPU is suspended. To be safe, the clockevents driver
cannot assume that timer IRQs will be received during CPU suspend.

Fixes: 62b01943 ("clocksource: new RISC-V SBI timer driver")
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20220509012121.40031-1-samuel@sholland.org


Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 41929c9f

drivers/clocksource/timer-riscv.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ static int riscv_clock_next_event(unsigned long delta, 
static unsigned int riscv_clock_event_irq;

static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {

	.name			= "riscv_timer_clockevent",

	.features		= CLOCK_EVT_FEAT_ONESHOT,

	.features		= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,

	.rating			= 100,

	.set_next_event		= riscv_clock_next_event,

};