Commit 231ad7a7 authored by David E. Box's avatar David E. Box Committed by Jia, Yingbao
Browse files

platform/x86/intel/vsec: Move structures to header

mainline inclusion
from mainline-v6.8
commit dbc01b0c86a7b23ffd06e14a84591500b04591ed
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IB6QCG
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dbc01b0c86a7b23ffd06e14a84591500b04591ed



-------------------------------------------------

Intel-SIG: commit dbc01b0c86a7 platform/x86/intel/vsec: Move structures to header.
Backport intel tpmi base driver update for 5.10

In preparation for exporting an API to register Intel Vendor Specific
Extended Capabilities (VSEC) from other drivers, move needed structures to
the header file.

Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20231129222132.2331261-4-david.e.box@linux.intel.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
[ Yingbao Jia: amend commit log ]
Signed-off-by: default avatarYingbao Jia <yingbao.jia@intel.com>
parent a3af58c1
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+0 −34
Original line number Diff line number Diff line
@@ -24,13 +24,6 @@

#include "intel_vsec.h"

/* Intel DVSEC offsets */
#define INTEL_DVSEC_ENTRIES		0xA
#define INTEL_DVSEC_SIZE		0xB
#define INTEL_DVSEC_TABLE		0xC
#define INTEL_DVSEC_TABLE_BAR(x)	((x) & GENMASK(2, 0))
#define INTEL_DVSEC_TABLE_OFFSET(x)	((x) & GENMASK(31, 3))
#define TABLE_OFFSET_SHIFT		3
#define PMT_XA_START			0
#define PMT_XA_MAX			INT_MAX
#define PMT_XA_LIMIT			XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
@@ -38,33 +31,6 @@
static DEFINE_IDA(intel_vsec_ida);
static DEFINE_XARRAY_ALLOC(auxdev_array);

/**
 * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
 * @rev:         Revision ID of the VSEC/DVSEC register space
 * @length:      Length of the VSEC/DVSEC register space
 * @id:          ID of the feature
 * @num_entries: Number of instances of the feature
 * @entry_size:  Size of the discovery table for each feature
 * @tbir:        BAR containing the discovery tables
 * @offset:      BAR offset of start of the first discovery table
 */
struct intel_vsec_header {
	u8	rev;
	u16	length;
	u16	id;
	u8	num_entries;
	u8	entry_size;
	u8	tbir;
	u32	offset;
};

enum intel_vsec_id {
	VSEC_ID_TELEMETRY	= 2,
	VSEC_ID_WATCHER		= 3,
	VSEC_ID_CRASHLOG	= 4,
	VSEC_ID_TPMI		= 66,
};

static const char *intel_vsec_name(enum intel_vsec_id id)
{
	switch (id) {
+35 −0
Original line number Diff line number Diff line
@@ -10,9 +10,44 @@
#define VSEC_CAP_CRASHLOG	BIT(2)
#define VSEC_CAP_TPMI		BIT(4)

/* Intel DVSEC offsets */
#define INTEL_DVSEC_ENTRIES            0xA
#define INTEL_DVSEC_SIZE               0xB
#define INTEL_DVSEC_TABLE              0xC
#define INTEL_DVSEC_TABLE_BAR(x)       ((x) & GENMASK(2, 0))
#define INTEL_DVSEC_TABLE_OFFSET(x)    ((x) & GENMASK(31, 3))
#define TABLE_OFFSET_SHIFT             3

struct pci_dev;
struct resource;

enum intel_vsec_id {
       VSEC_ID_TELEMETRY       = 2,
       VSEC_ID_WATCHER         = 3,
       VSEC_ID_CRASHLOG        = 4,
       VSEC_ID_TPMI            = 66,
};

/**
 * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
 * @rev:         Revision ID of the VSEC/DVSEC register space
 * @length:      Length of the VSEC/DVSEC register space
 * @id:          ID of the feature
 * @num_entries: Number of instances of the feature
 * @entry_size:  Size of the discovery table for each feature
 * @tbir:        BAR containing the discovery tables
 * @offset:      BAR offset of start of the first discovery table
 */
struct intel_vsec_header {
       u8      rev;
       u16     length;
       u16     id;
       u8      num_entries;
       u8      entry_size;
       u8      tbir;
       u32     offset;
};

enum intel_vsec_quirks {
	/* Watcher feature not supported */
	VSEC_QUIRK_NO_WATCHER	= BIT(0),