Commit 22e04325 authored Feb 24, 2021 by Ard Biesheuvel Committed by Zheng Zengkai Apr 08, 2021

ARM: decompressor: explicitly map decompressor binary cacheable

maillist inclusion
commit a58cdcfbee11974669a651e3ce049ef729e81411
category: feature
feature: ARM kaslr support
bugzilla: 47952
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/commit/?h=arm-kaslr-latest&id=a58cdcfbee11974669a651e3ce049ef729e81411



-------------------------------------------------

When randomizing the kernel load address, there may be a large
distance in memory between the decompressor binary and its payload
and the destination area in memory. Ensure that the decompressor
itself is mapped cacheable in this case, by tweaking the existing
routine that takes care of this for XIP decompressors.

Cc: Russell King <linux@armlinux.org.uk>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Cui GaoSheng <cuigaosheng1@huawei.com>
Reviewed-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>

parent 53645b5c

arch/arm/boot/compressed/head.S

+10 −6

Original line number	Diff line number	Diff line
		@@ -790,20 +790,24 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
		teq r0, r2
		bne 1b
		/*
		* If ever we are running from Flash, then we surely want the cache
		* to be enabled also for our execution instance... We map 2MB of it
		* so there is no map overlap problem for up to 1 MB compressed kernel.
		* If the execution is in RAM then we would only be duplicating the above.
		* Make sure our entire executable image (including payload) is mapped
		* cacheable, in case it is located outside the region we covered above.
		* (This may be the case if running from flash or with randomization enabled)
		* If the regions happen to overlap, we just duplicate some of the above.
		*/
		orr r1, r6, #0x04 @ ensure B is set for this
		orr r1, r1, #3 << 10
		mov r2, pc
		adr_l r9, _end
		mov r2, r2, lsr #20
		mov r9, r9, lsr #20
		orr r1, r1, r2, lsl #20
		add r0, r3, r2, lsl #2
		str r1, [r0], #4
		add r9, r3, r9, lsl #2
		0: str r1, [r0], #4
		add r1, r1, #1048576
		str r1, [r0]
		cmp r0, r9
		bls 0b
		mov pc, lr
		ENDPROC(__setup_mmu)