Commit 22c73ba4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2022-04-28' of... 

Merge tag 'drm-intel-fixes-2022-04-28' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Fix #5284: Backlight control regression on XMG Core 15 e21
- Fix black display plane on Acer One AO532h
- Two smaller display fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Ymotel5VfZUrJahf@jlahtine-mobl.ger.corp.intel.com
parents 43f2c104 f7e1089f

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

+26 −8
Original line number Diff line number Diff line
@@ -97,6 +97,14 @@ 


#define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_1                            0x359



enum intel_dp_aux_backlight_modparam {

	INTEL_DP_AUX_BACKLIGHT_AUTO = -1,

	INTEL_DP_AUX_BACKLIGHT_OFF = 0,

	INTEL_DP_AUX_BACKLIGHT_ON = 1,

	INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,

	INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,

};



/* Intel EDP backlight callbacks */

static bool

intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
@@ -126,6 +134,24 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) 
		return false;

	}



	/*

	 * If we don't have HDR static metadata there is no way to

	 * runtime detect used range for nits based control. For now

	 * do not use Intel proprietary eDP backlight control if we

	 * don't have this data in panel EDID. In case we find panel

	 * which supports only nits based control, but doesn't provide

	 * HDR static metadata we need to start maintaining table of

	 * ranges for such panels.

	 */

	if (i915->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&

	    !(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &

	      BIT(HDMI_STATIC_METADATA_TYPE1))) {

		drm_info(&i915->drm,

			 "Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n",

			 INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL);

		return false;

	}



	panel->backlight.edp.intel.sdr_uses_aux =

		tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
@@ -413,14 +439,6 @@ static const struct intel_panel_bl_funcs intel_dp_vesa_bl_funcs = { 
	.get = intel_dp_aux_vesa_get_backlight,

};



enum intel_dp_aux_backlight_modparam {

	INTEL_DP_AUX_BACKLIGHT_AUTO = -1,

	INTEL_DP_AUX_BACKLIGHT_OFF = 0,

	INTEL_DP_AUX_BACKLIGHT_ON = 1,

	INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,

	INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,

};



int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)

{

	struct drm_device *dev = connector->base.dev;

drivers/gpu/drm/i915/display/intel_fbc.c

+1 −1
Original line number Diff line number Diff line
@@ -1037,7 +1037,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, 
	struct intel_plane_state *plane_state =

		intel_atomic_get_new_plane_state(state, plane);

	const struct drm_framebuffer *fb = plane_state->hw.fb;

	struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);

	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

	const struct intel_crtc_state *crtc_state;

	struct intel_fbc *fbc = plane->fbc;

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -4345,12 +4345,12 @@ 
#define _DSPAADDR				0x70184

#define _DSPASTRIDE				0x70188

#define _DSPAPOS				0x7018C /* reserved */

#define   DISP_POS_Y_MASK		REG_GENMASK(31, 0)

#define   DISP_POS_Y_MASK		REG_GENMASK(31, 16)

#define   DISP_POS_Y(y)			REG_FIELD_PREP(DISP_POS_Y_MASK, (y))

#define   DISP_POS_X_MASK		REG_GENMASK(15, 0)

#define   DISP_POS_X(x)			REG_FIELD_PREP(DISP_POS_X_MASK, (x))

#define _DSPASIZE				0x70190

#define   DISP_HEIGHT_MASK		REG_GENMASK(31, 0)

#define   DISP_HEIGHT_MASK		REG_GENMASK(31, 16)

#define   DISP_HEIGHT(h)		REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))

#define   DISP_WIDTH_MASK		REG_GENMASK(15, 0)

#define   DISP_WIDTH(w)			REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
@@ -5152,7 +5152,7 @@ 
#define _SEL_FETCH_PLANE_BASE_6_A		0x70940

#define _SEL_FETCH_PLANE_BASE_7_A		0x70960

#define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880

#define _SEL_FETCH_PLANE_BASE_1_B		0x70990

#define _SEL_FETCH_PLANE_BASE_1_B		0x71890



#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \

					     _SEL_FETCH_PLANE_BASE_1_A, \