Commit 22c5aee3 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Daniel Vetter
Browse files

drm/i915: Fix drain latency precision multipler for VLV 



Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 843db716

drivers/gpu/drm/i915/i915_reg.h

+25 −25
Original line number Diff line number Diff line
@@ -3863,47 +3863,47 @@ enum punit_power_well { 


/* drain latency register values*/

#define DRAIN_LATENCY_PRECISION_32	32

#define DRAIN_LATENCY_PRECISION_16	16

#define DRAIN_LATENCY_PRECISION_64	64

#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)

#define DDL_CURSORA_PRECISION_32	(1<<31)

#define DDL_CURSORA_PRECISION_16	(0<<31)

#define DDL_CURSORA_PRECISION_64	(1<<31)

#define DDL_CURSORA_PRECISION_32	(0<<31)

#define DDL_CURSORA_SHIFT		24

#define DDL_SPRITEB_PRECISION_32	(1<<23)

#define DDL_SPRITEB_PRECISION_16	(0<<23)

#define DDL_SPRITEB_PRECISION_64	(1<<23)

#define DDL_SPRITEB_PRECISION_32	(0<<23)

#define DDL_SPRITEB_SHIFT		16

#define DDL_SPRITEA_PRECISION_32	(1<<15)

#define DDL_SPRITEA_PRECISION_16	(0<<15)

#define DDL_SPRITEA_PRECISION_64	(1<<15)

#define DDL_SPRITEA_PRECISION_32	(0<<15)

#define DDL_SPRITEA_SHIFT		8

#define DDL_PLANEA_PRECISION_32		(1<<7)

#define DDL_PLANEA_PRECISION_16		(0<<7)

#define DDL_PLANEA_PRECISION_64		(1<<7)

#define DDL_PLANEA_PRECISION_32		(0<<7)

#define DDL_PLANEA_SHIFT		0



#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)

#define DDL_CURSORB_PRECISION_32	(1<<31)

#define DDL_CURSORB_PRECISION_16	(0<<31)

#define DDL_CURSORB_PRECISION_64	(1<<31)

#define DDL_CURSORB_PRECISION_32	(0<<31)

#define DDL_CURSORB_SHIFT		24

#define DDL_SPRITED_PRECISION_32	(1<<23)

#define DDL_SPRITED_PRECISION_16	(0<<23)

#define DDL_SPRITED_PRECISION_64	(1<<23)

#define DDL_SPRITED_PRECISION_32	(0<<23)

#define DDL_SPRITED_SHIFT		16

#define DDL_SPRITEC_PRECISION_32	(1<<15)

#define DDL_SPRITEC_PRECISION_16	(0<<15)

#define DDL_SPRITEC_PRECISION_64	(1<<15)

#define DDL_SPRITEC_PRECISION_32	(0<<15)

#define DDL_SPRITEC_SHIFT		8

#define DDL_PLANEB_PRECISION_32		(1<<7)

#define DDL_PLANEB_PRECISION_16		(0<<7)

#define DDL_PLANEB_PRECISION_64		(1<<7)

#define DDL_PLANEB_PRECISION_32		(0<<7)

#define DDL_PLANEB_SHIFT		0



#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)

#define DDL_CURSORC_PRECISION_32	(1<<31)

#define DDL_CURSORC_PRECISION_16	(0<<31)

#define DDL_CURSORC_PRECISION_64	(1<<31)

#define DDL_CURSORC_PRECISION_32	(0<<31)

#define DDL_CURSORC_SHIFT		24

#define DDL_SPRITEF_PRECISION_32	(1<<23)

#define DDL_SPRITEF_PRECISION_16	(0<<23)

#define DDL_SPRITEF_PRECISION_64	(1<<23)

#define DDL_SPRITEF_PRECISION_32	(0<<23)

#define DDL_SPRITEF_SHIFT		16

#define DDL_SPRITEE_PRECISION_32	(1<<15)

#define DDL_SPRITEE_PRECISION_16	(0<<15)

#define DDL_SPRITEE_PRECISION_64	(1<<15)

#define DDL_SPRITEE_PRECISION_32	(0<<15)

#define DDL_SPRITEE_SHIFT		8

#define DDL_PLANEC_PRECISION_32		(1<<7)

#define DDL_PLANEC_PRECISION_16		(0<<7)

#define DDL_PLANEC_PRECISION_64		(1<<7)

#define DDL_PLANEC_PRECISION_32		(0<<7)

#define DDL_PLANEC_SHIFT		0



/* FIFO watermark sizes etc */

drivers/gpu/drm/i915/intel_pm.c

+6 −6
Original line number Diff line number Diff line
@@ -1288,13 +1288,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, 


	entries = (clock / 1000) * pixel_size;

	*plane_prec_mult = (entries > 256) ?

		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;

		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;

	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *

						     pixel_size);



	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */

	*cursor_prec_mult = (entries > 256) ?

		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;

		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;

	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);



	return true;
@@ -1320,9 +1320,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) 
	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,

				      &cursor_prec_mult, &cursora_dl)) {

		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;

			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;

		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;

			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;



		I915_WRITE(VLV_DDL1, cursora_prec |

				(cursora_dl << DDL_CURSORA_SHIFT) |
@@ -1333,9 +1333,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) 
	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,

				      &cursor_prec_mult, &cursorb_dl)) {

		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;

			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;

		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;

			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;



		I915_WRITE(VLV_DDL2, cursorb_prec |

				(cursorb_dl << DDL_CURSORB_SHIFT) |