Commit 226ab010 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.6-tag1' of... 

Merge tag 'renesas-clk-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add graphics clock support on RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3,
    M3-W, and M3-N SoCs
  - Add Clocked Serial Interface (CSI) clocks on RZ/V2M
  - Add PWM (MTU3) clock and reset on RZ/G2UL and RZ/Five
  - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a77965: Add 3DGE and ZG support
  clk: renesas: r8a7796: Add 3DGE and ZG support
  clk: renesas: r8a7795: Add 3DGE and ZG support
  clk: renesas: emev2: Remove obsolete clkdev registration
  clk: renesas: r9a07g043: Add MTU3a clock and reset entry
  clk: renesas: rzg2l: Simplify .determine_rate()
  clk: renesas: r9a09g011: Add CSI related clocks
  clk: renesas: r8a774b1: Add 3DGE and ZG support
  clk: renesas: r8a774e1: Add 3DGE and ZG support
  clk: renesas: r8a774a1: Add 3DGE and ZG support
  clk: renesas: rcar-gen3: Add support for ZG clock
parents 06c2afb8 dec57795

drivers/clk/renesas/clk-emev2.c

+0 −3
Original line number Diff line number Diff line
@@ -6,7 +6,6 @@ 
 * Copyright (C) 2012 Magnus Damm

 */

#include <linux/clk-provider.h>

#include <linux/clkdev.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>
@@ -74,7 +73,6 @@ static void __init emev2_smu_clkdiv_init(struct device_node *np) 
	clk = clk_register_divider(NULL, np->name, parent_name, 0,

				   smu_base + reg[0], reg[1], 8, 0, &lock);

	of_clk_add_provider(np, of_clk_src_simple_get, clk);

	clk_register_clkdev(clk, np->full_name, NULL);

	pr_debug("## %s %pOFn %p\n", __func__, np, clk);

}

CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
@@ -92,7 +90,6 @@ static void __init emev2_smu_gclk_init(struct device_node *np) 
	clk = clk_register_gate(NULL, np->name, parent_name, 0,

				smu_base + reg[0], reg[1], 0, &lock);

	of_clk_add_provider(np, of_clk_src_simple_get, clk);

	clk_register_clkdev(clk, np->full_name, NULL);

	pr_debug("## %s %pOFn %p\n", __func__, np, clk);

}

CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	/* Core Clock Outputs */

	DEF_GEN3_Z("z",		R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_GEN3_Z("zg",	R8A774A1_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),

	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {

	DEF_MOD("3dge",			 112,	R8A774A1_CLK_ZG),

	DEF_MOD("tmu4",			 121,	R8A774A1_CLK_S0D6),

	DEF_MOD("tmu3",			 122,	R8A774A1_CLK_S3D2),

	DEF_MOD("tmu2",			 123,	R8A774A1_CLK_S3D2),

drivers/clk/renesas/r8a774b1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 


	/* Core Clock Outputs */

	DEF_GEN3_Z("z",         R8A774B1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("zg",        R8A774B1_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),

	DEF_FIXED("ztr",        R8A774B1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774B1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {

	DEF_MOD("3dge",			 112,	R8A774B1_CLK_ZG),

	DEF_MOD("tmu4",			 121,	R8A774B1_CLK_S0D6),

	DEF_MOD("tmu3",			 122,	R8A774B1_CLK_S3D2),

	DEF_MOD("tmu2",			 123,	R8A774B1_CLK_S3D2),

drivers/clk/renesas/r8a774e1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { 
	/* Core Clock Outputs */

	DEF_GEN3_Z("z",		R8A774E1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",	R8A774E1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_GEN3_Z("zg",	R8A774E1_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),

	DEF_FIXED("ztr",        R8A774E1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774E1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {

	DEF_MOD("3dge",			 112,	R8A774E1_CLK_ZG),

	DEF_MOD("fdp1-1",		 118,	R8A774E1_CLK_S0D1),

	DEF_MOD("fdp1-0",		 119,	R8A774E1_CLK_S0D1),

	DEF_MOD("tmu4",			 121,	R8A774E1_CLK_S0D6),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	/* Core Clock Outputs */

	DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_GEN3_Z("zg",        R8A7795_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),

	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -128,6 +129,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
};



static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {

	DEF_MOD("3dge",			 112,	R8A7795_CLK_ZG),

	DEF_MOD("fdp1-1",		 118,	R8A7795_CLK_S0D1),

	DEF_MOD("fdp1-0",		 119,	R8A7795_CLK_S0D1),

	DEF_MOD("tmu4",			 121,	R8A7795_CLK_S0D6),