Commit 2267a195 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
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drm/amd/display: Disable DTB Ref Clock Switching in dcn32 



[How & Why]
To be enabled once PMFW supports it.

Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2cfe34e1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+4 −0
Original line number Diff line number Diff line
@@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct( 
	if (clk_mgr->base.dentist_vco_freq_khz == 0)

		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */



	if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {

		clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;

	}



	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {

		//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);

		//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;