Unverified Commit 2237604e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!600 The driver supports PCIe 4 TB BAR device allocation. 

Merge Pull Request from: @lujunhuaHW 
 

PCI: Support BAR sizes up to 8TB：
Current kernel reports that BARs larger than 128GB, e.g., this 4TB BAR, are disabled: pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000)
Increase the maximum BAR size from 128GB to 8TB for future expansion.

Detailed Description: 
The 1813 EP device requires 4 TB BAR space to meet the address requirements on the card side. A certain amount of space is reserved for future expansion. The space is increased to 8 TB.
 
 
Link:https://gitee.com/openeuler/kernel/pulls/600

 

Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents f7ecc8ac 92923e10

drivers/pci/setup-bus.c

+1 −1
Original line number Diff line number Diff line
@@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 
{

	struct pci_dev *dev;

	resource_size_t min_align, align, size, size0, size1;

	resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */

	resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */

	int order, max_order;

	struct resource *b_res = find_bus_resource_of_type(bus,

					mask | IORESOURCE_PREFETCH, type);