Unverified Commit 21f4e74e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!3275 arm64: kernel: disable CNP on LINXICORE9100 

Merge Pull Request from: @ci-robot 
 
PR sync from: Tong Tiangen <tongtiangen@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/BNVS24XU4NRYSH2OHEIHAVPP73XNRYM6/ 
 
https://gitee.com/openeuler/kernel/issues/I8M8F9 
 
Link:https://gitee.com/openeuler/kernel/pulls/3275

 

Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Reviewed-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 46122b92 21f0c85e

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -203,6 +203,8 @@ stable kernels. 
| Hisilicon      | Hip08 SMMU PMCG | #162001900      | N/A                         |

|                | Hip09 SMMU PMCG |                 |                             |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1158,6 +1158,17 @@ config HISILICON_ERRATUM_161600802 


	  If unsure, say Y.



config HISILICON_ERRATUM_162100125

	bool "Hisilicon erratum 162100125"

	default y

	help

	  On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when

	  TTBRx.CNP=1 differs from the standard ARM core. This causes issues when

	  tlb entries sharing between CPU cores. Avoid these issues by disabling

	  CNP support for Hisilicon LINXICORE9100 cores.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -395,6 +395,7 @@ CONFIG_CAVIUM_ERRATUM_30115=y 
CONFIG_CAVIUM_TX2_ERRATUM_219=y

CONFIG_FUJITSU_ERRATUM_010001=y

CONFIG_HISILICON_ERRATUM_161600802=y

CONFIG_HISILICON_ERRATUM_162100125=y

CONFIG_QCOM_FALKOR_ERRATUM_1003=y

CONFIG_QCOM_FALKOR_ERRATUM_1009=y

CONFIG_QCOM_QDF2400_ERRATUM_0065=y

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
#define FUJITSU_CPU_PART_A64FX		0x001



#define HISI_CPU_PART_TSV110		0xD01

#define HISI_CPU_PART_LINXICORE9100	0xD02



#define APPLE_CPU_PART_M1_ICESTORM	0x022

#define APPLE_CPU_PART_M1_FIRESTORM	0x023
@@ -180,6 +181,7 @@ 
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

arch/arm64/kernel/cpu_errata.c

+14 −0
Original line number Diff line number Diff line
@@ -282,6 +282,13 @@ static const struct midr_range cavium_erratum_30115_cpus[] = { 
};

#endif



#ifdef CONFIG_HISILICON_ERRATUM_162100125

static const struct midr_range hisilicon_erratum_162100125_cpus[] = {

	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),

	{},

};

#endif



#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {

	{
@@ -506,6 +513,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.cpu_enable = cpu_enable_trap_ctr_access,

	},

#ifdef CONFIG_HISILICON_ERRATUM_162100125

	{

		.desc = "Hisilicon erratum 162100125",

		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100125,

		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

	{

		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",