Commit 21e9f767 authored by Ben Widawsky's avatar Ben Widawsky Committed by Dan Williams
Browse files

cxl: Rename mem to pci 



As the driver has undergone development, it's become clear that the
majority [entirety?] of the current functionality in mem.c is actually a
layer encapsulating functionality exposed through PCI based
interactions. This layer can be used either in isolation or to provide
functionality for higher level functionality.

CXL capabilities exist in a parallel domain to PCIe. CXL devices are
enumerable and controllable via "legacy" PCIe mechanisms; however, their
CXL capabilities are a superset of PCIe. For example, a CXL device may
be connected to a non-CXL capable PCIe root port, and therefore will not
be able to participate in CXL.mem or CXL.cache operations, but can still
be accessed through PCIe mechanisms for CXL.io operations.

To properly represent the PCI nature of this driver, and in preparation for
introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
mem.c is available for this new driver.

The result of the change is that there is a clear layering distinction
in the driver, and a systems administrator may load only the cxl_pci
module and gain access to such operations as, firmware update, offline
provisioning of devices, and error collection. In addition to freeing up
the file name for another purpose, there are two primary reasons this is
useful,
    1. Acting upon devices which don't have full CXL capabilities. This
       may happen for instance if the CXL device is connected in a CXL
       unaware part of the platform topology.
    2. Userspace-first provisioning for devices without kernel driver
       interference. This may be useful when provisioning a new device
       in a specific manner that might otherwise be blocked or prevented
       by the real CXL mem driver.

Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/20210526174413.802913-1-ben.widawsky@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 35c32e30

Documentation/driver-api/cxl/memory-devices.rst

+3 −3
Original line number Diff line number Diff line
@@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device. 
CXL Memory Device

-----------------



.. kernel-doc:: drivers/cxl/mem.c

   :doc: cxl mem

.. kernel-doc:: drivers/cxl/pci.c

   :doc: cxl pci



.. kernel-doc:: drivers/cxl/mem.c

.. kernel-doc:: drivers/cxl/pci.c

   :internal:



CXL Core

drivers/cxl/Kconfig

+4 −9
Original line number Diff line number Diff line
@@ -21,15 +21,10 @@ config CXL_MEM 
	  as if the memory was attached to the typical CPU memory

	  controller.



	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as

	  a module) that will attach to CXL.mem devices for

	  configuration, provisioning, and health monitoring. This

	  driver is required for dynamic provisioning of CXL.mem

	  attached memory which is a prerequisite for persistent memory

	  support. Typically volatile memory is mapped by platform

	  firmware and included in the platform memory map, but in some

	  cases the OS is responsible for mapping that memory. See

	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.

	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for

	  configuration and management primarily via the mailbox interface. See

	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more

	  details.



	  If unsure say 'm'.

drivers/cxl/Makefile

+2 −2
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_CXL_BUS) += cxl_core.o

obj-$(CONFIG_CXL_MEM) += cxl_mem.o

obj-$(CONFIG_CXL_MEM) += cxl_pci.o



ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL

cxl_core-y := core.o

cxl_mem-y := mem.o
 
cxl_pci-y := pci.o

drivers/cxl/mem.c→drivers/cxl/pci.c

+4 −5
Original line number Diff line number Diff line
@@ -16,10 +16,11 @@ 
#include "mem.h"



/**

 * DOC: cxl mem

 * DOC: cxl pci

 *

 * This implements a CXL memory device ("type-3") as it is defined by the

 * Compute Express Link specification.

 * This implements the PCI exclusive functionality for a CXL device as it is

 * defined by the Compute Express Link specification. CXL devices may surface

 * certain functionality even if it isn't CXL enabled.

 *

 * The driver has several responsibilities, mainly:

 *  - Create the memX device and register on the CXL bus.
@@ -27,8 +28,6 @@ 
 *  - Probe the device attributes to establish sysfs interface.

 *  - Provide an IOCTL interface to userspace to communicate with the device for

 *    things like firmware update.

 *  - Support management of interleave sets.

 *  - Handle and manage error conditions.

 */



#define cxl_doorbell_busy(cxlm)                                                \