Commit 21c47196 authored by Anusha Srivatsa's avatar Anusha Srivatsa Committed by Lucas De Marchi
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drm/i915/dmc: Add MMIO range restrictions 



Bspec has added some steps that check forDMC MMIO range before
programming them

v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)

BSpec: 49193

Cc: stable@vger.kernel.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511000847.1068302-1-anusha.srivatsa@intel.com
parent 7ecc3cc8

drivers/gpu/drm/i915/display/intel_dmc.c

+44 −0
Original line number Diff line number Diff line
@@ -378,6 +378,44 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, 
	}

}



static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,

				       const u32 *mmioaddr, u32 mmio_count,

				       int header_ver, u8 dmc_id)

{

	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);

	u32 start_range, end_range;

	int i;



	if (dmc_id >= DMC_FW_MAX) {

		drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);

		return false;

	}



	if (header_ver == 1) {

		start_range = DMC_MMIO_START_RANGE;

		end_range = DMC_MMIO_END_RANGE;

	} else if (dmc_id == DMC_FW_MAIN) {

		start_range = TGL_MAIN_MMIO_START;

		end_range = TGL_MAIN_MMIO_END;

	} else if (DISPLAY_VER(i915) >= 13) {

		start_range = ADLP_PIPE_MMIO_START;

		end_range = ADLP_PIPE_MMIO_END;

	} else if (DISPLAY_VER(i915) >= 12) {

		start_range = TGL_PIPE_MMIO_START(dmc_id);

		end_range = TGL_PIPE_MMIO_END(dmc_id);

	} else {

		drm_warn(&i915->drm, "Unknown mmio range for sanity check");

		return false;

	}



	for (i = 0; i < mmio_count; i++) {

		if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)

			return false;

	}



	return true;

}



static u32 parse_dmc_fw_header(struct intel_dmc *dmc,

			       const struct intel_dmc_header_base *dmc_header,

			       size_t rem_size, u8 dmc_id)
@@ -447,6 +485,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 
		return 0;

	}



	if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,

					dmc_header->header_ver, dmc_id)) {

		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");

		return 0;

	}



	for (i = 0; i < mmio_count; i++) {

		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);

		dmc_info->mmiodata[i] = mmiodata[i];

drivers/gpu/drm/i915/display/intel_dmc_regs.h

+17 −1
Original line number Diff line number Diff line
@@ -17,6 +17,22 @@ 
#define DMC_LAST_WRITE_VALUE	0xc003b400

#define DMC_MMIO_START_RANGE	0x80000

#define DMC_MMIO_END_RANGE     0x8FFFF

#define DMC_V1_MMIO_START_RANGE		0x80000

#define TGL_MAIN_MMIO_START		0x8F000

#define TGL_MAIN_MMIO_END		0x8FFFF

#define _TGL_PIPEA_MMIO_START		0x92000

#define _TGL_PIPEA_MMIO_END		0x93FFF

#define _TGL_PIPEB_MMIO_START		0x96000

#define _TGL_PIPEB_MMIO_END		0x97FFF

#define ADLP_PIPE_MMIO_START		0x5F000

#define ADLP_PIPE_MMIO_END		0x5FFFF



#define TGL_PIPE_MMIO_START(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\

					      _TGL_PIPEB_MMIO_START)



#define TGL_PIPE_MMIO_END(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\

					      _TGL_PIPEB_MMIO_END)



#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)

#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)

#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)