Commit 219fa961 authored by Paul Hsieh's avatar Paul Hsieh Committed by Alex Deucher
Browse files

drm/amd/display: watermark latencies is not enough on DCN31 



[Why]
The original latencies were causing underflow in some modes.
Resolution: 2880x1620@60p when HDR enable

[How]
1. Replace with the up-to-date watermark values based on new measurments
2. Correct the ddr_wm_table name to DDR5 on DCN31

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarPaul Hsieh <paul.hsieh@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d389eafa

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+10 −10
Original line number Diff line number Diff line
@@ -329,38 +329,38 @@ static struct clk_bw_params dcn31_bw_params = { 


};



static struct wm_table ddr4_wm_table = {

static struct wm_table ddr5_wm_table = {

	.entries = {

		{

			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 6.09,

			.sr_enter_plus_exit_time_us = 7.14,

			.sr_exit_time_us = 9,

			.sr_enter_plus_exit_time_us = 11,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.sr_exit_time_us = 9,

			.sr_enter_plus_exit_time_us = 11,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.sr_exit_time_us = 9,

			.sr_enter_plus_exit_time_us = 11,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.sr_exit_time_us = 9,

			.sr_enter_plus_exit_time_us = 11,

			.valid = true,

		},

	}
@@ -687,7 +687,7 @@ void dcn31_clk_mgr_construct( 
		if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {

			dcn31_bw_params.wm_table = lpddr5_wm_table;

		} else {

			dcn31_bw_params.wm_table = ddr4_wm_table;

			dcn31_bw_params.wm_table = ddr5_wm_table;

		}

		/* Saved clocks configured at boot for debug purposes */

		 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);