Commit 2195c163 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/qcom-ep' 

- Log unknown Qcom Endpoint IRQ events at error level, not debug level
  (Manivannan Sadhasivam)

- Add DT and driver support for qcom interconnect bandwidth voting for
  "pcie-mem" and "cpu-pcie" interconnects (Krishna chaitanya chundru)

* pci/controller/qcom-ep:
  PCI: qcom-ep: Add ICC bandwidth voting support
  dt-bindings: PCI: qcom: ep: Add interconnects path
  PCI: qcom-ep: Treat unknown IRQ events as an error
parents e8ce465f 01794236

Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml

+15 −0
Original line number Diff line number Diff line
@@ -74,6 +74,14 @@ properties: 
    description: GPIO used as WAKE# output signal

    maxItems: 1



  interconnects:

    maxItems: 2



  interconnect-names:

    items:

      - const: pcie-mem

      - const: cpu-pcie



  resets:

    maxItems: 1
@@ -101,6 +109,8 @@ required: 
  - interrupts

  - interrupt-names

  - reset-gpios

  - interconnects

  - interconnect-names

  - resets

  - reset-names

  - power-domains
@@ -169,7 +179,9 @@ examples: 
  - |

    #include <dt-bindings/clock/qcom,gcc-sdx55.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sdx55.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    pcie_ep: pcie-ep@1c00000 {

        compatible = "qcom,sdx55-pcie-ep";

        reg = <0x01c00000 0x3000>,
@@ -196,6 +208,9 @@ examples: 
        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "global", "doorbell";

        interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,

                        <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;

        interconnect-names = "pcie-mem", "cpu-pcie";

        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;

        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;

        resets = <&gcc GCC_PCIE_BCR>;

drivers/pci/controller/dwc/pcie-qcom-ep.c

+73 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/debugfs.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/interconnect.h>

#include <linux/mfd/syscon.h>

#include <linux/phy/pcie.h>

#include <linux/phy/phy.h>
@@ -134,6 +135,11 @@ 
#define CORE_RESET_TIME_US_MAX			1005

#define WAKE_DELAY_US				2000 /* 2 ms */



#define PCIE_GEN1_BW_MBPS			250

#define PCIE_GEN2_BW_MBPS			500

#define PCIE_GEN3_BW_MBPS			985

#define PCIE_GEN4_BW_MBPS			1969



#define to_pcie_ep(x)				dev_get_drvdata((x)->dev)



enum qcom_pcie_ep_link_status {
@@ -156,6 +162,7 @@ enum qcom_pcie_ep_link_status { 
 * @wake: WAKE# GPIO

 * @phy: PHY controller block

 * @debugfs: PCIe Endpoint Debugfs directory

 * @icc_mem: Handle to an interconnect path between PCIe and MEM

 * @clks: PCIe clocks

 * @num_clks: PCIe clocks count

 * @perst_en: Flag for PERST enable
@@ -179,6 +186,8 @@ struct qcom_pcie_ep { 
	struct phy *phy;

	struct dentry *debugfs;



	struct icc_path *icc_mem;



	struct clk_bulk_data *clks;

	int num_clks;
@@ -254,8 +263,49 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 
	disable_irq(pcie_ep->perst_irq);

}



static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)

{

	struct dw_pcie *pci = &pcie_ep->pci;

	u32 offset, status, bw;

	int speed, width;

	int ret;



	if (!pcie_ep->icc_mem)

		return;



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);



	speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);

	width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);



	switch (speed) {

	case 1:

		bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);

		break;

	case 2:

		bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);

		break;

	case 3:

		bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);

		break;

	default:

		dev_warn(pci->dev, "using default GEN4 bandwidth\n");

		fallthrough;

	case 4:

		bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);

		break;

	}



	ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);

	if (ret)

		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",

			ret);

}



static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)

{

	struct dw_pcie *pci = &pcie_ep->pci;

	int ret;



	ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
@@ -278,8 +328,24 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 
	if (ret)

		goto err_phy_exit;



	/*

	 * Some Qualcomm platforms require interconnect bandwidth constraints

	 * to be set before enabling interconnect clocks.

	 *

	 * Set an initial peak bandwidth corresponding to single-lane Gen 1

	 * for the pcie-mem path.

	 */

	ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));

	if (ret) {

		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",

			ret);

		goto err_phy_off;

	}



	return 0;



err_phy_off:

	phy_power_off(pcie_ep->phy);

err_phy_exit:

	phy_exit(pcie_ep->phy);

err_disable_clk:
@@ -290,6 +356,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 


static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)

{

	icc_set_bw(pcie_ep->icc_mem, 0, 0);

	phy_power_off(pcie_ep->phy);

	phy_exit(pcie_ep->phy);

	clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
@@ -551,6 +618,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 
	if (IS_ERR(pcie_ep->phy))

		ret = PTR_ERR(pcie_ep->phy);



	pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");

	if (IS_ERR(pcie_ep->icc_mem))

		ret = PTR_ERR(pcie_ep->icc_mem);



	return ret;

}
@@ -574,6 +645,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 
	} else if (FIELD_GET(PARF_INT_ALL_BME, status)) {

		dev_dbg(dev, "Received BME event. Link is enabled!\n");

		pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;

		qcom_pcie_ep_icc_update(pcie_ep);

		pci_epc_bme_notify(pci->ep.epc);

	} else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {

		dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
@@ -594,7 +666,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 
		dw_pcie_ep_linkup(&pci->ep);

		pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;

	} else {

		dev_dbg(dev, "Received unknown event: %d\n", status);

		dev_err(dev, "Received unknown event: %d\n", status);

	}



	return IRQ_HANDLED;