Commit 217cf927 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Thomas Bogendoerfer
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mips: ralink: mt7620: define MT7620_SYSC_BASE with __iomem 



So that MT7620_SYSC_BASE can be used later in multiple functions without
needing to repeat this __iomem declaration each time

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 7a26b384

arch/mips/include/asm/mach-ralink/mt7620.h

+2 −1
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ 
#ifndef _MT7620_REGS_H_

#define _MT7620_REGS_H_



#define MT7620_SYSC_BASE		0x10000000

#define IOMEM(x)			((void __iomem *)(KSEG1ADDR(x)))

#define MT7620_SYSC_BASE		IOMEM(0x10000000)



#define SYSC_REG_CHIP_NAME0		0x00

#define SYSC_REG_CHIP_NAME1		0x04

arch/mips/ralink/mt7620.c

+7 −8
Original line number Diff line number Diff line
@@ -326,7 +326,6 @@ mt7628_dram_init(struct ralink_soc_info *soc_info) 


void __init prom_soc_init(struct ralink_soc_info *soc_info)

{

	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);

	unsigned char *name = NULL;

	u32 n0;

	u32 n1;
@@ -336,9 +335,9 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) 
	u32 pmu1;

	u32 bga;



	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);

	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);

	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);

	n0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);

	n1 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);

	rev = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);

	bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;



	if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
@@ -352,7 +351,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) 
			soc_info->compatible = "ralink,mt7620n-soc";

		}

	} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {

		u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);

		u32 efuse = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);



		if (efuse & EFUSE_MT7688) {

			ralink_soc = MT762X_SOC_MT7688;
@@ -372,7 +371,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) 
		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,

		(rev & CHIP_REV_ECO_MASK));



	cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);

	cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);

	if (is_mt76x8()) {

		dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;

	} else {
@@ -388,8 +387,8 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) 
	else

		mt7620_dram_init(soc_info);



	pmu0 = __raw_readl(sysc + PMU0_CFG);

	pmu1 = __raw_readl(sysc + PMU1_CFG);

	pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);

	pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);



	pr_info("Analog PMU set to %s control\n",

		(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));